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binutils-gdb/sim/testsuite/bfin/c_dagmodik_lnz_imltbl.s

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sim: bfin: import testsuite Now that the common sim testsuite code supports .S and .c files, we can import the Blackfin testsuite. There are about ~800 tests here, so I'm only attaching a compressed patch of them. Other than adding files to sim/testsuite/sim/bfin/, the sim/configure.tgt file was updated to mark Blackfin as having a testsuite, and sim/configure regenerated. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-05 01:44:22 +08:00
//Original:/testcases/core/c_dagmodik_lnz_imltbl/c_dagmodik_lnz_imltbl.dsp
// Spec Reference: dagmodik l not zero & i+m < b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000100e;
imm32 b1, 0x0000110c;
imm32 b2, 0x0000101a;
imm32 b3, 0x00001008;
imm32 l0, 0x000000a1;
imm32 l1, 0x000000b2;
imm32 l2, 0x000000c3;
imm32 l3, 0x000000d4;
imm32 m0, 0x00000005;
imm32 m1, 0x00000004;
imm32 m2, 0x00000003;
imm32 m3, 0x00000002;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001002;
CHECKREG r1, 0x00001102;
CHECKREG r2, 0x00001012;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001104;
CHECKREG r6, 0x00001014;
CHECKREG r7, 0x00001005;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x000010A3;
CHECKREG r1, 0x000011B4;
CHECKREG r2, 0x000010D5;
CHECKREG r3, 0x000010D7;
CHECKREG r4, 0x000010A1;
CHECKREG r5, 0x000011B2;
CHECKREG r6, 0x000010D3;
CHECKREG r7, 0x000010D5;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x000010A5;
CHECKREG r1, 0x000011B6;
CHECKREG r2, 0x000010D7;
CHECKREG r3, 0x000010D9;
CHECKREG r4, 0x000010A9;
CHECKREG r5, 0x000011BA;
CHECKREG r6, 0x000010DB;
CHECKREG r7, 0x00001009;
I0 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG r0, 0x000010A1;
CHECKREG r1, 0x000011B2;
CHECKREG r2, 0x000010D3;
CHECKREG r3, 0x000010D5;
CHECKREG r4, 0x000010A9;
CHECKREG r5, 0x000011BA;
CHECKREG r6, 0x000010DB;
CHECKREG r7, 0x00001009;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x000010A1;
CHECKREG r1, 0x000011B2;
CHECKREG r2, 0x000010D3;
CHECKREG r3, 0x000010D5;
CHECKREG r4, 0x00001099;
CHECKREG r5, 0x000011AA;
CHECKREG r6, 0x000010CB;
CHECKREG r7, 0x000010CD;
// i+m = b+l
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000100e;
imm32 b1, 0x0000110c;
imm32 b2, 0x0000101a;
imm32 b3, 0x00001008;
imm32 l0, 0x00000011;
imm32 l1, 0x00000012;
imm32 l2, 0x00000013;
imm32 l3, 0x00000014;
imm32 m0, 0x00000002;
imm32 m1, 0x00000003;
imm32 m2, 0x00000004;
imm32 m3, 0x00000005;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001002;
CHECKREG r1, 0x00001102;
CHECKREG r2, 0x00001012;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001104;
CHECKREG r6, 0x00001014;
CHECKREG r7, 0x00001005;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001013;
CHECKREG r1, 0x00001114;
CHECKREG r2, 0x00001025;
CHECKREG r3, 0x00001017;
CHECKREG r4, 0x00001011;
CHECKREG r5, 0x00001112;
CHECKREG r6, 0x00001023;
CHECKREG r7, 0x00001015;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001015;
CHECKREG r1, 0x00001116;
CHECKREG r2, 0x00001027;
CHECKREG r3, 0x00001019;
CHECKREG r4, 0x00001019;
CHECKREG r5, 0x0000111A;
CHECKREG r6, 0x0000102B;
CHECKREG r7, 0x00001009;
I0 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG r0, 0x00001011;
CHECKREG r1, 0x00001112;
CHECKREG r2, 0x00001023;
CHECKREG r3, 0x00001015;
CHECKREG r4, 0x00001019;
CHECKREG r5, 0x0000111A;
CHECKREG r6, 0x0000102B;
CHECKREG r7, 0x00001009;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001011;
CHECKREG r1, 0x00001112;
CHECKREG r2, 0x00001023;
CHECKREG r3, 0x00001015;
CHECKREG r4, 0x0000101A;
CHECKREG r5, 0x0000111C;
CHECKREG r6, 0x0000101B;
CHECKREG r7, 0x0000100D;
pass
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