mirror/binutils-gdb
2
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-12-27 04:52:05 +08:00
Code Issues Packages Projects Releases Wiki Activity
1e15fcac94
binutils-gdb/sim/testsuite/bfin/c_ccflag_pr_imm3.s

540 lines
8.6 KiB
ArmAsm
Raw Normal View History

sim: bfin: import testsuite Now that the common sim testsuite code supports .S and .c files, we can import the Blackfin testsuite. There are about ~800 tests here, so I'm only attaching a compressed patch of them. Other than adding files to sim/testsuite/sim/bfin/, the sim/configure.tgt file was updated to mark Blackfin as having a testsuite, and sim/configure regenerated. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-05 01:44:22 +08:00
//Original:/testcases/core/c_ccflag_pr_imm3/c_ccflag_pr_imm3.dsp
// Spec Reference: ccflag pr-imm3
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
//imm32 p0, 0x00000001;
imm32 p1, 0x00000001;
imm32 p2, 0x00000002;
imm32 p3, 0x00000003;
imm32 p4, 0x00000001;
imm32 p5, 0x00000002;
imm32 sp, 0x00000003;
imm32 fp, 0x00000003;
R0 = 0;
ASTAT = R0;
// positive dreg EQUAL to positive imm3
CC = P1 == 1;
R0 = ASTAT;
CC = P1 < 1;
R1 = ASTAT;
CC = P1 <= 1;
R2 = ASTAT;
CC = P2 == 2;
R3 = ASTAT;
CC = P2 < 2;
R4 = ASTAT;
CC = P2 <= 2;
R5 = ASTAT;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000020;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000020;
CC = P3 == 3;
R0 = ASTAT;
CC = P3 < 3;
R1 = ASTAT;
CC = P3 <= 3;
R2 = ASTAT;
CC = P4 == 1;
R3 = ASTAT;
CC = P4 < 1;
R4 = ASTAT;
CC = P4 <= 1;
R5 = ASTAT;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000020;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000020;
CC = P5 == 2;
R0 = ASTAT;
CC = P5 < 2;
R1 = ASTAT;
CC = P5 <= 2;
R2 = ASTAT;
CC = SP == 3;
R3 = ASTAT;
CC = SP < 3;
R4 = ASTAT;
CC = SP <= 3;
R5 = ASTAT;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000020;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000020;
CC = FP == 3;
R5 = ASTAT;
CC = FP < 3;
R6 = ASTAT;
CC = FP <= 3;
R7 = ASTAT;
CHECKREG r5, 0x00000020;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000020;
// positive dreg GREATER than positive imm3
imm32 p1, 0x00000002;
imm32 p2, 0x00000002;
imm32 p3, 0x00000003;
imm32 p4, 0x00000002;
imm32 p5, 0x00000002;
imm32 sp, 0x00000003;
imm32 fp, 0x00000003;
CC = P1 == 0;
R0 = ASTAT;
CC = P1 < 0;
R1 = ASTAT;
CC = P1 <= 0;
R2 = ASTAT;
CC = P2 == 1;
R3 = ASTAT;
CC = P2 < 1;
R4 = ASTAT;
CC = P2 <= 1;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = P3 == 2;
R0 = ASTAT;
CC = P3 < 2;
R1 = ASTAT;
CC = P3 <= 2;
R2 = ASTAT;
CC = P4 == 0;
R3 = ASTAT;
CC = P4 < 0;
R4 = ASTAT;
CC = P4 <= 0;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = P5 == 1;
R0 = ASTAT;
CC = P5 < 1;
R1 = ASTAT;
CC = P5 <= 1;
R2 = ASTAT;
CC = SP == 2;
R3 = ASTAT;
CC = SP < 2;
R4 = ASTAT;
CC = SP <= 2;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = FP == 2;
R5 = ASTAT;
CC = FP < 2;
R6 = ASTAT;
CC = FP <= 2;
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// positive dreg LESS than positive imm3
imm32 p1, 0x00000001;
imm32 p2, 0x00000002;
imm32 p3, 0x00000002;
imm32 p4, 0x00000001;
imm32 p5, 0x00000001;
imm32 sp, 0x00000002;
imm32 fp, 0x00000002;
CC = P1 == 2;
R0 = ASTAT;
CC = P1 < 2;
R1 = ASTAT;
CC = P1 <= 2;
R2 = ASTAT;
CC = P2 == 3;
R3 = ASTAT;
CC = P2 < 3;
R4 = ASTAT;
CC = P2 <= 3;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000020;
CC = P3 == 3;
R0 = ASTAT;
CC = P3 < 3;
R1 = ASTAT;
CC = P3 <= 3;
R2 = ASTAT;
CC = P4 == 3;
R3 = ASTAT;
CC = P4 < 3;
R4 = ASTAT;
CC = P4 <= 3;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000020;
CC = P5 == 3;
R0 = ASTAT;
CC = P5 < 3;
R1 = ASTAT;
CC = P5 <= 3;
R2 = ASTAT;
CC = SP == 3;
R3 = ASTAT;
CC = SP < 3;
R4 = ASTAT;
CC = SP <= 3;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000020;
CC = FP == 3;
R5 = ASTAT;
CC = FP < 3;
R6 = ASTAT;
CC = FP <= 3;
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000020;
// positive dreg GREATER than neg imm3
CC = P1 == -1;
R0 = ASTAT;
CC = P1 < -1;
R1 = ASTAT;
CC = P1 <= -1;
R2 = ASTAT;
CC = P2 == -2;
R3 = ASTAT;
CC = P2 < -2;
R4 = ASTAT;
CC = P2 <= -2;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = P3 == -3;
R0 = ASTAT;
CC = P3 < -3;
R1 = ASTAT;
CC = P3 <= -3;
R2 = ASTAT;
CC = P4 == -4;
R3 = ASTAT;
CC = P4 < -4;
R4 = ASTAT;
CC = P4 <= -4;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = P5 == -1;
R0 = ASTAT;
CC = P5 < -1;
R1 = ASTAT;
CC = P5 <= -1;
R2 = ASTAT;
CC = SP == -2;
R3 = ASTAT;
CC = SP < -2;
R4 = ASTAT;
CC = SP <= -2;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = FP == -4;
R5 = ASTAT;
CC = FP < -4;
R6 = ASTAT;
CC = FP <= -4;
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 p1, -1;
imm32 p2, -2;
imm32 p3, -3;
imm32 p4, -4;
imm32 p5, -1;
imm32 sp, -2;
imm32 fp, -3;
// negative dreg equal negative imm3
CC = P1 == -1;
R0 = ASTAT;
CC = P1 < -1;
R1 = ASTAT;
CC = P1 <= -1;
R2 = ASTAT;
CC = P2 == -2;
R3 = ASTAT;
CC = P2 < -2;
R4 = ASTAT;
CC = P2 <= -2;
R5 = ASTAT;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000020;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000020;
CC = P3 == -3;
R0 = ASTAT;
CC = P3 < -3;
R1 = ASTAT;
CC = P3 <= -3;
R2 = ASTAT;
CC = P4 == -4;
R3 = ASTAT;
CC = P4 < -4;
R4 = ASTAT;
CC = P4 <= -4;
R5 = ASTAT;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000020;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000020;
CC = P5 == -1;
R0 = ASTAT;
CC = P5 < -1;
R1 = ASTAT;
CC = P5 <= -1;
R2 = ASTAT;
CC = SP == -2;
R3 = ASTAT;
CC = SP < -2;
R4 = ASTAT;
CC = SP <= -2;
R5 = ASTAT;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000020;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000020;
CC = FP == -3;
R5 = ASTAT;
CC = FP < -3;
R6 = ASTAT;
CC = FP <= -3;
R7 = ASTAT;
CHECKREG r5, 0x00000020;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000020;
// negative dreg GREATER neg imm3
imm32 p1, -1;
imm32 p2, -1;
imm32 p3, -2;
imm32 p4, -3;
imm32 p5, -1;
imm32 sp, -2;
imm32 fp, -3;
CC = P1 == -2;
R0 = ASTAT;
CC = P1 < -2;
R1 = ASTAT;
CC = P1 <= -2;
R2 = ASTAT;
CC = P2 == -3;
R3 = ASTAT;
CC = P2 < -3;
R4 = ASTAT;
CC = P2 <= -3;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = P3 == -4;
R0 = ASTAT;
CC = P3 < -4;
R1 = ASTAT;
CC = P3 <= -4;
R2 = ASTAT;
CC = P4 == -4;
R3 = ASTAT;
CC = P4 < -4;
R4 = ASTAT;
CC = P4 <= -4;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = P5 == -2;
R0 = ASTAT;
CC = P5 < -2;
R1 = ASTAT;
CC = P5 <= -2;
R2 = ASTAT;
CC = SP == -3;
R3 = ASTAT;
CC = SP < -3;
R4 = ASTAT;
CC = SP <= -3;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = FP == -4;
R5 = ASTAT;
CC = FP < -4;
R6 = ASTAT;
CC = FP <= -4;
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// negative dreg LESS than neg imm3
imm32 p1, -2;
imm32 p2, -2;
imm32 p3, -3;
imm32 p4, -3;
imm32 p5, -4;
imm32 sp, -4;
imm32 fp, -4;
imm32 p4, -4;
CC = P1 == -1;
R0 = ASTAT;
CC = P1 < -1;
R1 = ASTAT;
CC = P1 <= -1;
R2 = ASTAT;
CC = P2 == -1;
R3 = ASTAT;
CC = P2 < -1;
R4 = ASTAT;
CC = P2 <= -1;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000020;
CC = P3 == -2;
R0 = ASTAT;
CC = P3 < -2;
R1 = ASTAT;
CC = P3 <= -2;
R2 = ASTAT;
CC = P4 == -2;
R3 = ASTAT;
CC = P4 < -2;
R4 = ASTAT;
CC = P4 <= -2;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000020;
CC = P5 == -3;
R0 = ASTAT;
CC = P5 < -3;
R1 = ASTAT;
CC = P5 <= -3;
R2 = ASTAT;
CC = SP == -3;
R3 = ASTAT;
CC = SP < -3;
R4 = ASTAT;
CC = SP <= -3;
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000020;
CC = FP == -3;
R5 = ASTAT;
CC = FP < -3;
R6 = ASTAT;
CC = FP <= -3;
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000020;
pass
Reference in New Issue Copy Permalink