binutils-gdb/ld/testsuite/ld-tic6x/pcrel-reloc-global-rel.d

#name: C6X PC-relative relocations, global symbols, REL
#as: -mlittle-endian -mgenerate-rel
#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s7a=0x0fffff00 --defsym s7b=0x100000fc --defsym s10a=0x0ffff800 --defsym s10b=0x100007fc --defsym s12a=0x0fffe000 --defsym s12b=0x10001ffc --defsym s21a=0x0fc00000 --defsym s21b=0x103ffffc
#source: pcrel-reloc-global.s
#objdump: -dr

.*: *file format elf32-tic6x-le


Disassembly of section \.text:

10000000 <[^>]*>:
10000000:[ \t]+00c00162[ \t]+addkpc \.S2 fffff00 <[^>]*>,b1,0
10000004:[ \t]+00bf0162[ \t]+addkpc \.S2 100000fc <[^>]*>,b1,0
10000008:[ \t]+08000012[ \t]+b \.S2 fc00000 <[^>]*>
1000000c:[ \t]+07ffff92[ \t]+b \.S2 103ffffc <[^>]*>
10000010:[ \t]+00c01022[ \t]+bdec \.S2 ffff800 <[^>]*>,b1
10000014:[ \t]+00bff022[ \t]+bdec \.S2 100007fc <[^>]*>,b1
10000018:[ \t]+08000122[ \t]+bnop \.S2 fffe000 <[^>]*>,0
1000001c:[ \t]+07ff0122[ \t]+bnop \.S2 10001ffc <[^>]*>,0
bfd: * elf32-tic6x.h: New. * elf-bfd.h (enum elf_target_id): Define TIC6X_ELF_DATA. * elf32-tic6x.c (struct elf32_tic6x_obj_tdata, elf32_tic6x_tdata, elf32_tic6x_howto_table_rel, elf32_tic6x_info_to_howto_rel, elf32_tic6x_set_use_rela_p, elf32_tic6x_mkobject, elf32_tic6x_new_section_hook, elf32_tic6x_rel_relocation_p, bfd_elf32_mkobject, bfd_elf32_new_section_hook): New. (elf32_tic6x_reloc_type_lookup, elf32_tic6x_reloc_name_lookup, elf32_tic6x_relocate_section): Handle REL relocations. (elf_info_to_howto_rel): Define to elf32_tic6x_info_to_howto_rel. gas: * config/tc-tic6x.c (OPTION_MGENERATE_REL): New. (md_longopts): Add -mgenerate-rel. (tic6x_generate_rela): New. (md_parse_option): Handle -mgenerate-rel. (md_show_usage): Add comment that -mgenerate-rel is undocumented. (tic6x_init_after_args): New. (md_apply_fix): Correct shift calculations for SB-relative relocations. (md_pcrel_from): Change to tic6x_pcrel_from_section. Do not adjust addresses for relocations referencing symbols in other sections. (tc_gen_reloc): Adjust addend calculations for REL relocations. * config/tc-tic6x.h (MD_PCREL_FROM_SECTION, tic6x_pcrel_from_section, tc_init_after_args, tic6x_init_after_args): New. ld/testsuite: * ld-tic6x/data-reloc-global-rel.d, ld-tic6x/data-reloc-global-rel.s, ld-tic6x/data-reloc-local-r-rel.d, ld-tic6x/data-reloc-local-rel.d, ld-tic6x/mvk-reloc-global-rel.d, ld-tic6x/mvk-reloc-global-rel.s, ld-tic6x/mvk-reloc-local-1-rel.s, ld-tic6x/mvk-reloc-local-2-rel.s, ld-tic6x/mvk-reloc-local-r-rel.d, ld-tic6x/mvk-reloc-local-rel.d, ld-tic6x/pcrel-reloc-global-rel.d, ld-tic6x/pcrel-reloc-local-r-rel.d, ld-tic6x/pcrel-reloc-local-rel.d, ld-tic6x/sbr-reloc-global-rel.d, ld-tic6x/sbr-reloc-global-rel.s, ld-tic6x/sbr-reloc-local-1-rel.s, ld-tic6x/sbr-reloc-local-2-rel.s, ld-tic6x/sbr-reloc-local-r-rel.d, ld-tic6x/sbr-reloc-local-rel.d: New. 2010-04-21 06:03:00 +08:00			`#name: C6X PC-relative relocations, global symbols, REL`
			`#as: -mlittle-endian -mgenerate-rel`
			`#ld: -melf32_tic6x_le -Tgeneric.ld --defsym s7a=0x0fffff00 --defsym s7b=0x100000fc --defsym s10a=0x0ffff800 --defsym s10b=0x100007fc --defsym s12a=0x0fffe000 --defsym s12b=0x10001ffc --defsym s21a=0x0fc00000 --defsym s21b=0x103ffffc`
			`#source: pcrel-reloc-global.s`
			`#objdump: -dr`

			`.: file format elf32-tic6x-le`


			`Disassembly of section \.text:`

			`10000000 <[^>]*>:`
			`10000000:[ \t]+00c00162[ \t]+addkpc \.S2 fffff00 <[^>]*>,b1,0`
			`10000004:[ \t]+00bf0162[ \t]+addkpc \.S2 100000fc <[^>]*>,b1,0`
			`10000008:[ \t]+08000012[ \t]+b \.S2 fc00000 <[^>]*>`
			`1000000c:[ \t]+07ffff92[ \t]+b \.S2 103ffffc <[^>]*>`
			`10000010:[ \t]+00c01022[ \t]+bdec \.S2 ffff800 <[^>]*>,b1`
			`10000014:[ \t]+00bff022[ \t]+bdec \.S2 100007fc <[^>]*>,b1`
			`10000018:[ \t]+08000122[ \t]+bnop \.S2 fffe000 <[^>]*>,0`
			`1000001c:[ \t]+07ff0122[ \t]+bnop \.S2 10001ffc <[^>]*>,0`