2016-09-21 23:57:22 +08:00
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (double_precision_operand_p): New function.
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(parse_operands): Use it to calculate the dp_p input to
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parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
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[AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands. There are
three kinds:
- simple signed and unsigned ranges, but with new widths and positions.
- 13-bit logical immediates. These have the same form as in base AArch64,
but at a different bit position.
In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
immediate <limm> is not allowed to be a valid DUP immediate, since DUP
is preferred over DUPM for constants that both instructions can handle.
- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
In some contexts the operand is signed and in others it's unsigned.
As an extension, we allow shifted immediates to be written as a single
integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the
shiftless form as the preferred disassembly, except for the special
case of "#0, LSL #8" (a redundant encoding of 0).
include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.
2016-09-21 23:56:57 +08:00
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
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immediate operands.
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[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
This patch adds support for addresses of the form:
[<base>, #<offset>, MUL VL]
This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.
For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, .... The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
operands.
* aarch64-opc.c (aarch64_operand_modifiers): Initialize
the AARCH64_MOD_MUL_VL entry.
(value_aligned_p): Cope with non-power-of-two alignments.
(operand_general_constraint_met_p): Handle the new MUL VL addresses.
(print_immediate_offset_address): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
(ins_sve_addr_ri_s9xvl): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
(ext_sve_addr_ri_s9xvl): New extractors.
* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
parse_shift_modes.
(parse_shift): Handle SHIFTED_MUL_VL.
(parse_address_main): Add an imm_shift_mode parameter.
(parse_address, parse_sve_address): Update accordingly.
(parse_operands): Handle MUL VL addressing modes.
2016-09-21 23:56:15 +08:00
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
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parse_shift_modes.
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(parse_shift): Handle SHIFTED_MUL_VL.
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(parse_address_main): Add an imm_shift_mode parameter.
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(parse_address, parse_sve_address): Update accordingly.
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(parse_operands): Handle MUL VL addressing modes.
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[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 23:55:49 +08:00
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
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register types.
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(get_reg_expected_msg): Handle them.
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(aarch64_addr_reg_parse): New function, split out from
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aarch64_reg_parse_32_64. Handle Z registers too.
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(aarch64_reg_parse_32_64): Call it.
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(parse_address_main): Add base_qualifier, offset_qualifier,
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base_type and offset_type parameters. Handle SVE base and offset
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registers.
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(parse_address): Update call to parse_address_main.
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(parse_sve_address): New function.
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(parse_operands): Parse the new SVE address operands.
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[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
2016-09-21 23:55:22 +08:00
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
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(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
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shift modes. Skip range tests for AARCH64_MOD_MUL.
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(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
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(parse_operands): Likewise.
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2016-09-21 23:54:53 +08:00
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (parse_enum_string): New function.
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(po_enum_or_fail): New macro.
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(parse_operands): Handle AARCH64_OPND_SVE_PATTERN and
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AARCH64_OPND_SVE_PRFOP.
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2016-09-21 23:54:30 +08:00
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
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(parse_vector_type_for_operand): Assert that the skipped character
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is a '.'.
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(parse_predication_for_operand): New function.
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(parse_typed_reg): Parse /z and /m suffixes for predicate registers.
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(vectype_to_qualifier): Handle NT_zero and NT_merge.
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[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 23:53:54 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
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|
|
|
|
|
|
|
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
|
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|
|
|
(AARCH64_REG_TYPES): Add ZN and PN.
|
|
|
|
|
|
(get_reg_expected_msg): Handle them.
|
|
|
|
|
|
(parse_vector_type_for_operand): Add a reg_type parameter.
|
|
|
|
|
|
Skip the width for Zn and Pn registers.
|
|
|
|
|
|
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
|
|
|
|
|
|
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
|
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|
|
|
expecting the width to be 0.
|
|
|
|
|
|
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
|
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|
|
|
REG_TYPE_VN.
|
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|
|
|
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
|
|
|
|
|
|
(parse_operands): Handle the new Zn and Pn operands.
|
|
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|
|
|
(REGSET16): New macro, split out from...
|
|
|
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|
|
(REGSET31): ...here.
|
|
|
|
|
|
(reg_names): Add Zn and Pn entries.
|
|
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|
|
[AArch64][SVE 20/32] Add support for tied operands
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.
The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.
include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.
gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
2016-09-21 23:52:30 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
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|
|
|
|
|
* config/tc-aarch64.c (output_operand_error_record): Handle
|
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|
|
AARCH64_OPDE_UNTIED_OPERAND.
|
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|
2016-09-21 23:51:00 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
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|
|
|
|
* config/tc-aarch64.c (find_best_match): Simplify, allowing an
|
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|
|
|
|
instruction with all-NIL qualifiers to fail to match.
|
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|
|
[AArch64][SVE 12/32] Remove boolean parameters from parse_address_main
In the review of the original version of this series, Richard didn't
like the use of boolean parameters to parse_address_main. I think we
can just get rid of them and leave the callers to check the addressing
modes. As it happens, the handling of ADDR_SIMM9{,_2} already did this
for relocation operators (i.e. it used parse_address_reloc and then
rejected relocations).
The callers are already set up to reject invalid register post-indexed
addressing, so we can simply remove the accept_reg_post_index parameter
without adding any more checks. This again creates a corner case where:
.equ x2, 1
ldr w0, [x1], x2
was previously an acceptable way of writing "ldr w0, [x1], #1" but
is now rejected.
Removing the "reloc" parameter means that two cases need to check
explicitly for relocation operators.
ADDR_SIMM9_2 appers to be unused. I'll send a separate patch
to remove it.
This patch makes parse_address temporarily equivalent to
parse_address_main, but later patches in the series will need
to keep the distinction.
gas/
* config/tc-aarch64.c (parse_address_main): Remove reloc and
accept_reg_post_index parameters. Parse relocations and register
post indexes unconditionally.
(parse_address): Remove accept_reg_post_index parameter.
Update call to parse_address_main.
(parse_address_reloc): Delete.
(parse_operands): Call parse_address instead of parse_address_main.
Update existing callers of parse_address and make them check
inst.reloc.type where appropriate.
* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
Also test for invalid uses of post-index register addressing.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
2016-09-21 23:49:31 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (parse_address_main): Remove reloc and
|
|
|
|
|
|
accept_reg_post_index parameters. Parse relocations and register
|
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|
|
|
|
post indexes unconditionally.
|
|
|
|
|
|
(parse_address): Remove accept_reg_post_index parameter.
|
|
|
|
|
|
Update call to parse_address_main.
|
|
|
|
|
|
(parse_address_reloc): Delete.
|
|
|
|
|
|
(parse_operands): Call parse_address instead of parse_address_main.
|
|
|
|
|
|
Update existing callers of parse_address and make them check
|
|
|
|
|
|
inst.reloc.type where appropriate.
|
|
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|
|
* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
|
|
|
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|
|
in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
|
|
|
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|
|
Also test for invalid uses of post-index register addressing.
|
|
|
|
|
|
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
|
|
|
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|
|
|
[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interface
aarch64_reg_parse_32_64 is currently used to parse address registers,
among other things. It returns two bits of information about the
register: whether it's W rather than X, and whether it's a zero register.
SVE adds addressing modes in which the base or offset can be a vector
register instead of a scalar, so a choice between W and X is no longer
enough. It's more convenient to pass the type of register around as
a qualifier instead.
As it happens, two callers of aarch64_reg_parse_32_64 already wanted
the information in the form of a qualifier, so the change feels pretty
natural even without SVE.
Also, the function took two parameters to control whether {W}SP
and (W|X)ZR should be accepted. We tend to get slightly better
error messages by accepting them regardless and getting the caller
to do the check, rather than potentially treating "xzr", "sp" etc.
as constants. This is easier to do if the function returns the
reg_entry rather than just the register number.
This does create a corner case where:
.equ sp, 1
ldr w0, [x0, sp]
was previously an acceptable way of writing "ldr w0, [x0, #1]",
but I don't think it's important to continue supporting that.
We already rejected things like:
.equ sp, 1
add x0, x1, sp
To ensure these new error messages "win" when matching against
several candidate instruction entries, we need to use the same
address-parsing code for all addresses, including ADDR_SIMPLE
and SIMD_ADDR_SIMPLE. The next patch also relies on this.
Finally, aarcch64_check_reg_type was written in a pretty
conservative way. It should always be equivalent to a single
bit test.
gas/
* config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
types.
(get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
(aarch64_check_reg_type): Simplify.
(aarch64_reg_parse_32_64): Return the reg_entry instead of the
register number. Return the type as a qualifier rather than an
"isreg32" boolean. Remove reject_sp, reject_rz and isregzero
parameters.
(parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
Use get_reg_expected_msg.
(parse_address_main): Likewise. Use aarch64_check_reg_type.
(po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
with a reg_type parameter. Update call to aarch64_parse_32_64_reg.
Use aarch64_check_reg_type to test the result.
(parse_operands): Update after the above changes. Parse ADDR_SIMPLE
addresses normally before enforcing the syntax restrictions.
* testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
zero register and for a stack pointer index.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
Also update existing diagnostic messages after the above changes.
* testsuite/gas/aarch64/illegal-lse.l: Update the error message
for 32-bit register bases.
2016-09-21 23:49:24 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
|
|
|
|
|
|
types.
|
|
|
|
|
|
(get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
|
|
|
|
|
|
(aarch64_check_reg_type): Simplify.
|
|
|
|
|
|
(aarch64_reg_parse_32_64): Return the reg_entry instead of the
|
|
|
|
|
|
register number. Return the type as a qualifier rather than an
|
|
|
|
|
|
"isreg32" boolean. Remove reject_sp, reject_rz and isregzero
|
|
|
|
|
|
parameters.
|
|
|
|
|
|
(parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
|
|
|
|
|
|
Use get_reg_expected_msg.
|
|
|
|
|
|
(parse_address_main): Likewise. Use aarch64_check_reg_type.
|
|
|
|
|
|
(po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
|
|
|
|
|
|
with a reg_type parameter. Update call to aarch64_parse_32_64_reg.
|
|
|
|
|
|
Use aarch64_check_reg_type to test the result.
|
|
|
|
|
|
(parse_operands): Update after the above changes. Parse ADDR_SIMPLE
|
|
|
|
|
|
addresses normally before enforcing the syntax restrictions.
|
|
|
|
|
|
* testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
|
|
|
|
|
|
zero register and for a stack pointer index.
|
|
|
|
|
|
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
|
|
|
|
|
|
Also update existing diagnostic messages after the above changes.
|
|
|
|
|
|
* testsuite/gas/aarch64/illegal-lse.l: Update the error message
|
|
|
|
|
|
for 32-bit register bases.
|
|
|
|
|
|
|
2016-09-21 23:49:15 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check.
|
|
|
|
|
|
(parse_operands): Check the range of 8-bit FP immediates here instead.
|
|
|
|
|
|
|
2016-09-21 23:49:07 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific
|
|
|
|
|
|
low-severity error for registers.
|
|
|
|
|
|
(parse_operands): Report an invalid floating point constant for
|
|
|
|
|
|
if parsing an FPIMM8 fails, and if no better error has been
|
|
|
|
|
|
recorded.
|
|
|
|
|
|
* testsuite/gas/aarch64/diagnostic.s,
|
|
|
|
|
|
testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands
|
|
|
|
|
|
to FMOV.
|
|
|
|
|
|
|
2016-09-21 23:48:59 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename
|
|
|
|
|
|
to...
|
|
|
|
|
|
(can_convert_double_to_float): ...this. Accept any double-precision
|
|
|
|
|
|
value that converts to single precision without loss of precision.
|
|
|
|
|
|
(parse_aarch64_imm_float): Update accordingly.
|
|
|
|
|
|
|
[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V
To remove parsing ambiguities and to avoid register names being
accidentally added to the symbol table, the immediate parsing
routines reject things like:
.equ x0, 0
add v0.4s, v0.4s, x0
An explicit '#' must be used instead:
.equ x0, 0
add v0.4s, v0.4s, #x0
Of course, it wasn't possible to predict what other register
names might be added in future, so this behaviour was restricted
to the register names that were defined at the time. For backwards
compatibility, we should continue to allow things like:
.equ p0, 0
add v0.4s, v0.4s, p0
even though p0 is now an SVE register.
However, it seems reasonable to extend the x0 behaviour above to
SVE registers when parsing SVE instructions, especially since none
of the SVE immediate formats are relocatable. Doing so removes the
same parsing ambiguity for SVE instructions as the x0 behaviour removes
for base AArch64 instructions.
As a prerequisite, we then need to be able to tell the parsing routines
which registers to reject. This patch changes the interface to make
that possible, although the set of rejected registers doesn't change
at this stage.
gas/
* config/tc-aarch64.c (parse_immediate_expression): Add a
reg_type parameter.
(parse_constant_immediate): Likewise, and update calls.
(parse_aarch64_imm_float): Likewise.
(parse_big_immediate): Likewise.
(po_imm_nc_or_fail): Update accordingly, passing down a new
imm_reg_type variable.
(po_imm_of_fail): Likewise.
(parse_operands): Likewise.
2016-09-21 23:48:50 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (parse_immediate_expression): Add a
|
|
|
|
|
|
reg_type parameter.
|
|
|
|
|
|
(parse_constant_immediate): Likewise, and update calls.
|
|
|
|
|
|
(parse_aarch64_imm_float): Likewise.
|
|
|
|
|
|
(parse_big_immediate): Likewise.
|
|
|
|
|
|
(po_imm_nc_or_fail): Update accordingly, passing down a new
|
|
|
|
|
|
imm_reg_type variable.
|
|
|
|
|
|
(po_imm_of_fail): Likewise.
|
|
|
|
|
|
(parse_operands): Likewise.
|
|
|
|
|
|
|
2016-09-21 23:48:41 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (parse_neon_reg_list): Rename to...
|
|
|
|
|
|
(parse_vector_reg_list): ...this and take a register type
|
|
|
|
|
|
as input.
|
|
|
|
|
|
(parse_operands): Update accordingly.
|
|
|
|
|
|
|
2016-09-21 23:48:34 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (parse_neon_type_for_operand): Rename to...
|
|
|
|
|
|
(parse_vector_type_for_operand): ...this.
|
|
|
|
|
|
(parse_typed_reg): Update accordingly.
|
|
|
|
|
|
|
2016-09-21 23:48:25 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (neon_type_el): Rename to...
|
|
|
|
|
|
(vector_type_el): ...this.
|
|
|
|
|
|
(parse_neon_type_for_operand): Update accordingly.
|
|
|
|
|
|
(parse_typed_reg): Likewise.
|
|
|
|
|
|
(aarch64_reg_parse): Likewise.
|
|
|
|
|
|
(vectype_to_qualifier): Likewise.
|
|
|
|
|
|
(parse_operands): Likewise.
|
|
|
|
|
|
(eq_neon_type_el): Likewise. Rename to...
|
|
|
|
|
|
(eq_vector_type_el): ...this.
|
|
|
|
|
|
(parse_neon_reg_list): Update accordingly.
|
|
|
|
|
|
|
2016-09-21 23:48:16 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (neon_el_type: Rename to...
|
|
|
|
|
|
(vector_el_type): ...this.
|
|
|
|
|
|
(neon_type_el): Update accordingly.
|
|
|
|
|
|
(parse_neon_type_for_operand): Likewise.
|
|
|
|
|
|
(vectype_to_qualifier): Likewise.
|
|
|
|
|
|
|
2016-09-21 23:47:57 +08:00
|
|
|
|
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (parse_neon_operand_type): Delete.
|
|
|
|
|
|
(parse_typed_reg): Call parse_neon_type_for_operand directly.
|
|
|
|
|
|
|
2016-09-15 18:24:24 +08:00
|
|
|
|
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/textinsnxop.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/textinsnxop.s: Likewise.
|
|
|
|
|
|
|
2016-09-15 18:20:54 +08:00
|
|
|
|
2016-09-15 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run
|
|
|
|
|
|
dcti-couples-v9 only in ELF targets to avoid spurious failures in
|
|
|
|
|
|
sparc-aout and sparc-coff targets.
|
|
|
|
|
|
|
Modify POWER9 support to match final ISA 3.0 documentation.
opcodes/
* ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
xor3>: Delete mnemonics.
<cp_abort>: Rename mnemonic from ...
<cpabort>: ...to this.
<setb>: Change to a X form instruction.
<sync>: Change to 1 operand form.
<copy>: Delete mnemonic.
<copy_first>: Rename mnemonic from ...
<copy>: ...to this.
<paste, paste.>: Delete mnemonics.
<paste_last>: Rename mnemonic from ...
<paste.>: ...to this.
gas/
* testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests.
<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests.
<copy, paste.>: Update tests.
* testsuite/gas/ppc/power9.s: Likewise.
2016-09-15 11:10:51 +08:00
|
|
|
|
2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests.
|
|
|
|
|
|
<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
|
|
|
|
|
|
xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests.
|
|
|
|
|
|
<copy, paste.>: Update tests.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.s: Likewise.
|
|
|
|
|
|
|
2016-09-14 22:15:24 +08:00
|
|
|
|
2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (sparc_ip): Print the instruction arguments
|
|
|
|
|
|
in "architecture mismatch" error messages.
|
|
|
|
|
|
|
2016-09-14 22:10:49 +08:00
|
|
|
|
2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (md_assemble): Detect and warning on
|
|
|
|
|
|
unpredictable DCTI couples in certain arches.
|
|
|
|
|
|
(dcti_couples_detect): New global.
|
|
|
|
|
|
(md_longopts): Add command line option -dcti-couples-detect.
|
|
|
|
|
|
(md_show_usage): Document -dcti-couples-detect.
|
|
|
|
|
|
(md_parse_option): Handle OPTION_DCTI_COUPLES_DETECT.
|
|
|
|
|
|
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run
|
|
|
|
|
|
dcti-couples-v8, dcti-couples-v9 and dcti-couples-v9c tests.
|
|
|
|
|
|
* testsuite/gas/sparc/dcti-couples.s: New file.
|
|
|
|
|
|
* testsuite/gas/sparc/dcti-couples-v9c.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/dcti-couples-v8.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/dcti-couples-v9.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/dcti-couples-v9c.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/dcti-couples-v8.l: Likewise.
|
|
|
|
|
|
* doc/as.texinfo (Overview): Document --dcti-couples-detect.
|
|
|
|
|
|
* doc/c-sparc.texi (Sparc-Opts): Likewise.
|
|
|
|
|
|
|
2016-09-07 15:47:34 +08:00
|
|
|
|
2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/tls-relocs2.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/tls-relocs2.s: Likewise.
|
|
|
|
|
|
* config/tc-arc.c (tokenize_arguments): Accept offsets when base
|
|
|
|
|
|
is used.
|
|
|
|
|
|
|
2016-09-12 22:32:02 +08:00
|
|
|
|
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-s390.c (s390_parse_cpu): Support alternate arch
|
|
|
|
|
|
strings.
|
|
|
|
|
|
* doc/as.texinfo: Document new arch strings.
|
|
|
|
|
|
* doc/c-s390.texi: Likewise.
|
|
|
|
|
|
|
2016-09-12 22:32:02 +08:00
|
|
|
|
2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-s390.c: Set all facitily bits by default
|
|
|
|
|
|
|
2016-09-12 22:32:02 +08:00
|
|
|
|
2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/s390/zarch-z196.d: Adjust testcase.
|
|
|
|
|
|
|
2016-09-08 22:54:16 +08:00
|
|
|
|
2016-09-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (i386_target_format): Allow PROCESSOR_IAMCU
|
|
|
|
|
|
for Intel MCU.
|
|
|
|
|
|
|
2016-09-08 00:16:25 +08:00
|
|
|
|
2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (valid_iamcu_cpu_flags): Removed.
|
|
|
|
|
|
(set_cpu_arch): Updated.
|
|
|
|
|
|
(md_parse_option): Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5. Remove
|
|
|
|
|
|
iamcu-inval-2 and iamcu-inval-3.
|
|
|
|
|
|
* testsuite/gas/i386/iamcu-4.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/iamcu-4.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/iamcu-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/iamcu-5.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/iamcu-inval-2.l: Removed.
|
|
|
|
|
|
* testsuite/gas/i386/iamcu-inval-2.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/iamcu-inval-3.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/iamcu-inval-3.s: Likewise.
|
|
|
|
|
|
|
2016-09-08 00:14:54 +08:00
|
|
|
|
2016-09-07 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c ((arm_cpus): Use ARM_ARCH_V8A_CRC for all
|
|
|
|
|
|
ARMv8-A CPUs except xgene1.
|
|
|
|
|
|
|
2016-08-31 11:48:34 +08:00
|
|
|
|
2016-08-31 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (md_assemble): Set sh_flags for VLE. Test
|
|
|
|
|
|
ppc_cpu rather than calling ppc_mach to determine VLE mode.
|
|
|
|
|
|
(ppc_frag_check, ppc_handle_align): Likewise use ppc_cpu.
|
|
|
|
|
|
|
2016-08-26 22:31:31 +08:00
|
|
|
|
2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/sparc/crypto.d: Rename invalid opcode camellia_fi
|
|
|
|
|
|
to camellia_fl.
|
|
|
|
|
|
* testsuite/gas/sparc/crypto.s: Likewise.
|
|
|
|
|
|
|
Add missing ARMv8-M special registers
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
their lowecase counterpart special registers. Write register
identifier in hex.
* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
operation, special register and then case. Use different register for
each operation. Add tests for new special registers.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
accordingly.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
opcodes/
* arm-dis.c (psr_name): Use hex as case labels. Add detection for
MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
2016-08-26 18:53:30 +08:00
|
|
|
|
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
|
|
|
|
|
|
PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
|
|
|
|
|
|
their lowecase counterpart special registers. Write register
|
|
|
|
|
|
identifier in hex.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
|
|
|
|
|
|
operation, special register and then case. Use different register for
|
|
|
|
|
|
each operation. Add tests for new special registers.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
|
|
|
|
|
|
accordingly.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
|
|
|
|
|
|
|
2016-08-25 16:44:09 +08:00
|
|
|
|
2016-08-25 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (v7m_psrs): Remove msp_s, MSP_S, psp_s and PSP_S
|
|
|
|
|
|
special registers.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr.s: Remove test for above special
|
|
|
|
|
|
registers.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
|
|
|
|
|
|
|
2016-08-25 06:27:11 +08:00
|
|
|
|
2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .ptwrite.
|
|
|
|
|
|
* doc/c-i386.texi: Document ptwrite and .ptwrite.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel,
|
|
|
|
|
|
x86-64-ptwrite and x86-64-ptwrite-intel.
|
|
|
|
|
|
* testsuite/gas/i386/ptwrite-intel.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/ptwrite.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/ptwrite.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-ptwrite.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-ptwrite.s: Likewise.
|
|
|
|
|
|
|
2016-08-19 19:57:20 +08:00
|
|
|
|
2016-08-19 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (do_co_reg2c): Added constraint.
|
|
|
|
|
|
* testsuite/gas/arm/dest-unpredictable.s: New.
|
|
|
|
|
|
* testsuite/gas/arm/dest-unpredictable.l: New.
|
|
|
|
|
|
* testsuite/gas/arm/dest-unpredictable.d: New.
|
|
|
|
|
|
|
2016-08-19 16:16:30 +08:00
|
|
|
|
2016-08-19 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Adjust expected
|
|
|
|
|
|
ordering of sections.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-unwind.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/alias-ilp32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/alias.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/group-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/group-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/secname-ilp32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/secname.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/unwind-ilp32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/unwind.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/xdata-ilp32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ia64/xdata.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mmix/bspec-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mmix/bspec-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mmix/byte-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mmix/loc-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mmix/loc-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mmix/loc-3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mmix/loc-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mmix/loc-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
|
|
|
|
|
|
|
2016-08-11 16:14:45 +08:00
|
|
|
|
2016-08-11 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (parse_aarch64_imm_float): Reject -0.0.
|
|
|
|
|
|
* testsuite/gas/aarch64/illegal.s, testsuite/gas/aarch64/illegal.l:
|
|
|
|
|
|
Add tests for -0.0. Add an end-of-file comment.
|
|
|
|
|
|
|
2016-08-05 17:37:57 +08:00
|
|
|
|
2016-08-05 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
2016-08-05 18:26:13 +08:00
|
|
|
|
PR gas/20429
|
|
|
|
|
|
* config/tc-arm.c (do_vfp_nsyn_push): Check that no more than 16
|
|
|
|
|
|
registers are pushed.
|
|
|
|
|
|
(do_vfp_nsyn_pop): Check that no more than 16 registers are
|
|
|
|
|
|
popped.
|
|
|
|
|
|
* testsuite/gas/arm/pr20429.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/pr20429.d: New test driver.
|
|
|
|
|
|
* testsuite/gas/arm/pr20429.1: Expected error output.
|
|
|
|
|
|
|
2016-08-05 17:37:57 +08:00
|
|
|
|
PR gas/20364
|
|
|
|
|
|
* config/tc-aarch64.c (s_ltorg): Change the mapping state after
|
|
|
|
|
|
aligning the frag.
|
|
|
|
|
|
(aarch64_init): Treat rs_align frags in code sections as
|
|
|
|
|
|
containing code, not data.
|
|
|
|
|
|
* testsuite/gas/aarch64/pr20364.s: New test.
|
|
|
|
|
|
* testsuite/gas/aarch64/pr20364.d: New test driver.
|
|
|
|
|
|
|
2016-08-04 21:57:23 +08:00
|
|
|
|
2016-08-04 Stefan Trleman <stefan.teleman@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20427
|
|
|
|
|
|
* config/tc-sparc.c (cons_fix_new_sparc): Prevent the generation
|
|
|
|
|
|
of 64-bit relocation types when assembling for a 32-bit Solaris
|
|
|
|
|
|
target.
|
|
|
|
|
|
|
gas: avoid spurious failures in non-ELF targets in the SPARC testsuite.
Many of the existing sparc tests fail in non-ELF targets (coff and
a.out) due to spurious differences in the expected results:
- Unlike ELF, a.out text sections are aligned to 2**3 and padded
accordingly. The padding instruction is a `nop' (01 00 00 00).
- Likewise, coff text sections are also aligned to 2**3 and padded
accordingly. However, the padding instruction in these targets is an
`illtrap 0' (00 00 00 00).
- Unlike ELF, a.out and coff binaries don't contain hardware
capabilities bits that could be used by BFD to determine the opcodes
architecture corresponding to the instructions encoded in the
objects (v9, v9a, v9b, v9c, etc). Consequently, in both a.out and
coff tests we would need to pass proper `-m sparc:vXXX' options when
invoking objdump before comparing results.
In order to fix these issues, the most obvious solution would be to have
three variants of .d files per impacted test. For example, for save.d
we would have: save-elf.d, save-aout.d and save-coff.d. Using the
`#source' directive, a single save.s file would provide the input for
all of them. However, this approach has the following problems:
- The #target and #notarget .d directives are very limited: they use
globs instead of regular expressions, and thus it is not possible (or
too messy) to use them to discriminate between elf, coff and a.out
sparc targets.
- It adds little or no value to have variants of all these tests for all
the target types, and it would be a burden to maintain them. Actually
the features tested in the spuriously failing tests (relatively modern
sparc instructions, registers and asis) are not really found in
running coff or a.out sparc systems.
This patch changes sparc.exp so it will run these tests only in
ELF-targets, using the more standard `is_elf_format' from
binutils-common.exp instead of the ad-hoc (and less convenient, as it
must be called before _every_ single elf-only test) sparc_elf_setup.
Incidentally, the patch also fixes the #name entry for save-args.d.
Tested in sparc*-*-linux-gnu, sparc-aout and sparc-coff targets.
gas/ChangeLog:
2016-07-27 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc.exp: Use is_elf_format to discriminate
ELF targets.
Run natural, natural-32, pr4587, ticc-imm-reg, v8-movwr-imm,
pause, save-args, cbcond, cfr, crypto edge, flush, hpcvis3, ima,
ld_st_fsr, ldtw_sttw, ldd_std, ldx_stx, ldx_efsr, mwait, mcdper,
sparc5vis4, xcrypto, v9branch1 and imm-plus-rreg only in ELF
targets.
(sparc_elf_setup): Delete.
* testsuite/gas/sparc/save-args.d: Fix a copy-paste typo in the
test's #name entry.
2016-07-27 21:59:16 +08:00
|
|
|
|
2016-07-27 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/sparc/sparc.exp: Use is_elf_format to discriminate
|
|
|
|
|
|
ELF targets.
|
|
|
|
|
|
Run natural, natural-32, pr4587, ticc-imm-reg, v8-movwr-imm,
|
|
|
|
|
|
pause, save-args, cbcond, cfr, crypto edge, flush, hpcvis3, ima,
|
|
|
|
|
|
ld_st_fsr, ldtw_sttw, ldd_std, ldx_stx, ldx_efsr, mwait, mcdper,
|
|
|
|
|
|
sparc5vis4, xcrypto, v9branch1 and imm-plus-rreg only in ELF
|
|
|
|
|
|
targets.
|
|
|
|
|
|
(sparc_elf_setup): Delete.
|
|
|
|
|
|
* testsuite/gas/sparc/save-args.d: Fix a copy-paste typo in the
|
|
|
|
|
|
test's #name entry.
|
|
|
|
|
|
|
MIPS/GAS: Implement microMIPS branch/jump compaction
Convert microMIPS branches and jumps whose delay slot would be filled by
a generated NOP instruction to the corresponding compact form where one
exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap.
Do so even where the transformation switches from a 16-bit to a 32-bit
branch encoding for no benefit in code size reduction, as this is still
advantageous. This is because a branch/NOP pair takes 2 pipeline slots
or a 2-cycle completion latency except in superscalar implementations.
Whereas a compact branch may or may not stall on its target fetch, so it
will at most have a 2-cycle completion latency and may have only 1 even
in scalar implementations, and in superscalar implementations it is
expected to have no worse latency as a branch/NOP pair has. Also it
won't stall and therefore take the extra latency cycle in the not-taken
case.
Technically this is the same as MIPS16 compaction: for the qualifying
instruction encodings the APPEND_ADD_COMPACT machine code generation
method is selected where APPEND_ADD_WITH_NOP otherwise would and tells
the code generator in `append_insn' to convert the regular form of an
instruction to its corresponding compact form. For this the opcode is
tweaked as necessary and the microMIPS opcode table is scanned for the
matching updated instruction. A non-$0 `rt' operand to BEQ and BNE
instructions is moved to the `rs' operand field of BEQZC and BNEZC
encodings as required.
Unlike with MIPS16 compaction however we need to handle out-of-distance
branch relaxation as well. We do this by deferring the generation of
any delay-slot NOP required to relaxation made in `md_convert_frag', by
converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD
where a relaxed instruction is recorded. Relaxation then, depending on
actual code produced, chooses between either using a compact branch or
jump encoding and emitting the NOP outstanding if no compact encoding is
possible.
For code simplicity's sake the relaxation pass is retained even if the
principle of preferring a compact encoding to a 16-bit branch/NOP pair
means, in the absence of out-of-range branch relaxation, that a single
compact branch machine code instruction will eventually be produced from
a given assembly source instruction.
gas/
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
(get_append_method): Also return APPEND_ADD_COMPACT for
microMIPS instructions.
(find_altered_mips16_opcode): Exclude macros from matching.
Factor code out...
(find_altered_opcode): ... to this new function.
(find_altered_micromips_opcode): New function.
(frag_branch_delay_slot_size): Likewise.
(append_insn): Handle microMIPS branch/jump compaction.
(macro_start): Likewise.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
for delay slot filling.
* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
delay slot filling.
* testsuite/gas/mips/micromips-size-1.s: Likewise.
* testsuite/gas/mips/micromips.l: Adjust line numbers.
* testsuite/gas/mips/micromips-warn.l: Likewise.
* testsuite/gas/mips/micromips-size-1.l: Likewise.
* testsuite/gas/mips/micromips.d: Adjust padding.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips@beq.d: Update patterns for
branch/jump compaction.
* testsuite/gas/mips/micromips@bge.d: Likewise.
* testsuite/gas/mips/micromips@bgeu.d: Likewise.
* testsuite/gas/mips/micromips@blt.d: Likewise.
* testsuite/gas/mips/micromips@bltu.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
Likewise.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
* testsuite/gas/mips/micromips@relax.d: Likewise.
* testsuite/gas/mips/micromips@relax-at.d: Likewise.
* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
* testsuite/gas/mips/branch-extern-2.d: Likewise.
* testsuite/gas/mips/branch-extern-4.d: Likewise.
* testsuite/gas/mips/branch-section-2.d: Likewise.
* testsuite/gas/mips/branch-section-4.d: Likewise.
* testsuite/gas/mips/branch-weak-2.d: Likewise.
* testsuite/gas/mips/branch-weak-5.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/micromips-compact.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
ld/
* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
patterns for branch compaction.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
Likewise.
opcodes/
* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
"j".
2016-07-28 00:27:55 +08:00
|
|
|
|
2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
|
|
|
|
|
|
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
|
|
|
|
|
|
(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
|
|
|
|
|
|
(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
|
|
|
|
|
|
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
|
|
|
|
|
|
(get_append_method): Also return APPEND_ADD_COMPACT for
|
|
|
|
|
|
microMIPS instructions.
|
|
|
|
|
|
(find_altered_mips16_opcode): Exclude macros from matching.
|
|
|
|
|
|
Factor code out...
|
|
|
|
|
|
(find_altered_opcode): ... to this new function.
|
|
|
|
|
|
(find_altered_micromips_opcode): New function.
|
|
|
|
|
|
(frag_branch_delay_slot_size): Likewise.
|
|
|
|
|
|
(append_insn): Handle microMIPS branch/jump compaction.
|
|
|
|
|
|
(macro_start): Likewise.
|
|
|
|
|
|
(relaxed_micromips_32bit_branch_length): Likewise.
|
|
|
|
|
|
(md_convert_frag): Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
|
|
|
|
|
|
for delay slot filling.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
|
|
|
|
|
|
delay slot filling.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-size-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips.l: Adjust line numbers.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-warn.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-size-1.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips.d: Adjust padding.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-trap.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-insn32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@beq.d: Update patterns for
|
|
|
|
|
|
branch/jump compaction.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@bge.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@bgeu.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@blt.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@bltu.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@relax.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@relax-at.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-extern-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-extern-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-section-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-section-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-addend.d:
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-compact.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new test.
|
|
|
|
|
|
|
2016-07-27 22:57:18 +08:00
|
|
|
|
2016-07-27 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c: Add new global arc_addrtype_hash.
|
|
|
|
|
|
Define O_colon and O_addrtype.
|
|
|
|
|
|
(debug_exp): Add O_colon and O_addrtype.
|
|
|
|
|
|
(tokenize_arguments): Handle colon and address type
|
|
|
|
|
|
tokens.
|
|
|
|
|
|
(declare_addrtype): New function.
|
|
|
|
|
|
(md_begin): Initialise arc_addrtype_hash.
|
|
|
|
|
|
(arc_parse_name): Add lookup of address types.
|
|
|
|
|
|
(assemble_insn): Handle colons and address types by
|
|
|
|
|
|
ignoring them.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-8.s: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-8.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-8.d: Add expected PMU
|
|
|
|
|
|
instruction output.
|
|
|
|
|
|
|
2016-07-27 00:50:55 +08:00
|
|
|
|
2016-07-26 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `insn32' flag.
|
|
|
|
|
|
(RELAX_MICROMIPS_INSN32): New macro.
|
|
|
|
|
|
(RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT)
|
|
|
|
|
|
(RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_RELAX32)
|
|
|
|
|
|
(RELAX_MICROMIPS_TOOFAR16, RELAX_MICROMIPS_MARK_TOOFAR16)
|
|
|
|
|
|
(RELAX_MICROMIPS_CLEAR_TOOFAR16, RELAX_MICROMIPS_TOOFAR32)
|
|
|
|
|
|
(RELAX_MICROMIPS_MARK_TOOFAR32, RELAX_MICROMIPS_CLEAR_TOOFAR32):
|
|
|
|
|
|
Shift bits.
|
|
|
|
|
|
(append_insn): Record `mips_opts.insn32' with relaxed microMIPS
|
|
|
|
|
|
branches.
|
|
|
|
|
|
(relaxed_micromips_32bit_branch_length): Handle the `insn32'
|
|
|
|
|
|
mode.
|
|
|
|
|
|
(md_convert_frag): Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-relax.s: Add `insn32'
|
|
|
|
|
|
conditionals.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-relax.l: Update line
|
|
|
|
|
|
numbers accordingly.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-relax-pic.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-relax-insn32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-relax-insn32-pic.d: New
|
|
|
|
|
|
test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-relax-insn32.l: New
|
|
|
|
|
|
stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-relax-insn32-pic.l: New
|
|
|
|
|
|
stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-07-22 06:22:13 +08:00
|
|
|
|
2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
|
2016-07-21 00:08:07 +08:00
|
|
|
|
2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/dsp.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/dsp.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/fpu.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/fpu.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/ext2op.d: Add specific disassembler option.
|
|
|
|
|
|
* testsuite/gas/arc/ext3op.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/tdpfp.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/tfpuda.d: Likewise.
|
|
|
|
|
|
|
2016-07-20 19:11:52 +08:00
|
|
|
|
2016-07-20 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_force_relocation): Remove
|
|
|
|
|
|
R_MIPS_PC26_S2 and R_MIPS_PC21_S2.
|
|
|
|
|
|
|
2016-07-19 23:19:19 +08:00
|
|
|
|
2016-07-19 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_force_relocation, mips_fix_adjustable):
|
|
|
|
|
|
Adjust comments for BAL to JALX linker conversion.
|
|
|
|
|
|
(fix_bad_cross_mode_branch_p): Accept cross-mode BAL.
|
|
|
|
|
|
* testsuite/gas/mips/unaligned-branch-1.l: Update error messages
|
|
|
|
|
|
expected.
|
|
|
|
|
|
* testsuite/gas/mips/unaligned-branch-micromips-1.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-n32-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-n64-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-addend.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-addend-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-addend-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-4.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/branch-addend.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
MIPS: Verify the ISA mode and alignment of branch and jump targets
Verify that the ISA mode of branch targets is the same as the referring
relocation, so that an attempt to produce a branch between instructions
encoded in different ISA modes each causes an error rather than silently
producing non-functional code. Make sure that no symbol or addend bits
are silently truncated: terminate with an error if the relocation value
calculated cannot be encoded in the relocatable field of a branch; for
REL targets also applying to any intermediate addend.
Also make jump target's alignment verification consistent with that for
branches.
This change will require an update to some obscure handcoded assembly
sources which make branches to labels placed at data objects, however
for microMIPS code only. These labels will have to be updated with the
`.insn' directive for containing code to assemble and link successfully.
Such code is broken as any such labels have always been required by the
microMIPS architecture specification[1][2] to be annotated this way for
correct interpretation, and with our old code missing `.insn' directives
caused labels to present different semantics depending on whether they
were referred with branch (ISA bit ignored) or other relocations (ISA
bit respected).
Enforcing these checks however will ensure errors in building software,
like mixed regular MIPS and microMIPS code links with branches between,
will be diagnosed at the build time rather than causing odd run-time
errors such as intermittent crashes. It will also let cross-mode BAL
instructions be converted to JALX instructions, with a separate change.
References:
[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level
Compatibility", p. 533
[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level
Compatibility", p. 623
bfd/
* elfxx-mips.c (b_reloc_p): Add R_MICROMIPS_PC16_S1,
R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC7_S1.
(branch_reloc_p): New function.
(mips_elf_calculate_relocation): Handle ISA mode determination
for relocations against section symbols, against absolute
symbols and absolute relocations. Also set `*cross_mode_jump_p'
for branches.
<R_MIPS16_26, R_MIPS_26, R_MICROMIPS_26_S1>: Suppress alignment
checks for weak undefined symbols. Also check target alignment
within the same ISA mode.
<R_MIPS_PC16, R_MIPS_GNU_REL16_S2>: Handle cross-mode branches
in the alignment check.
<R_MICROMIPS_PC7_S1>: Add an alignment check.
<R_MICROMIPS_PC10_S1>: Likewise.
<R_MICROMIPS_PC16_S1>: Likewise.
(mips_elf_perform_relocation): Report a failure for unsupported
same-mode JALX instructions and cross-mode branches.
(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add
error messages for jumps to misaligned addresses.
gas/
* config/tc-mips.c (mips_force_relocation): Also retain branch
relocations against MIPS16 and microMIPS symbols.
(fix_bad_cross_mode_jump_p): New function.
(fix_bad_same_mode_jalx_p): Likewise.
(fix_bad_misaligned_jump_p): Likewise.
(fix_bad_cross_mode_branch_p): Likewise.
(fix_bad_misaligned_branch_p): Likewise.
(fix_validate_branch): Likewise.
(md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP>
<BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5,
etc. Verify the ISA mode and alignment of the jump target.
<BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check
with a call to `fix_validate_branch'.
<BFD_RELOC_MIPS_26_PCREL_S2>: Likewise.
<BFD_RELOC_16_PCREL_S2>: Likewise.
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend.
Verify the ISA mode and alignment of the branch target.
(md_convert_frag): Verify the ISA mode and alignment of resolved
MIPS16 branch targets.
* testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction
branch targets with `.insn'.
* testsuite/gas/mips/branch-misc-5.s: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Update
accordingly.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips-branch-relax.s: Annotate
non-instruction branch target with `.insn'.
* testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets
with external symbols.
* testsuite/gas/mips/micromips-insn32.d: Update accordingly.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips.d: Likewise.
* testsuite/gas/mips/mips16.s: Annotate non-instruction branch
targets with `.insn'.
* testsuite/gas/mips/mips16.d: Update accordingly.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction
branch target with `.insn'.
* testsuite/gas/mips/relax-swap3.s: Likewise.
* testsuite/gas/mips/branch-local-2.l: New list test.
* testsuite/gas/mips/branch-local-3.l: New list test.
* testsuite/gas/mips/branch-local-n32-2.l: New list test.
* testsuite/gas/mips/branch-local-n32-3.l: New list test.
* testsuite/gas/mips/branch-local-n64-2.l: New list test.
* testsuite/gas/mips/branch-local-n64-3.l: New list test.
* testsuite/gas/mips/unaligned-jump-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-3.d: New test.
* testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-jump-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-3.d: New test.
* testsuite/gas/mips/unaligned-branch-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-3.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-3.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-4.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-5.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-6.d: New test.
* testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-branch-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-3.d: New test.
* testsuite/gas/mips/branch-local-2.s: New test source.
* testsuite/gas/mips/branch-local-3.s: New test source.
* testsuite/gas/mips/branch-local-n32-2.s: New test source.
* testsuite/gas/mips/branch-local-n32-3.s: New test source.
* testsuite/gas/mips/branch-local-n64-2.s: New test source.
* testsuite/gas/mips/branch-local-n64-3.s: New test source.
* testsuite/gas/mips/unaligned-jump-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-jump-micromips-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-3.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-4.s: New test source.
* testsuite/gas/mips/unaligned-branch-mips16-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-mips16-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-2.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error message
expected.
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise.
* testsuite/ld-mips-elf/undefweak-overflow.s: Add jumps,
microMIPS BAL and MIPS16 instructions.
* testsuite/ld-mips-elf/undefweak-overflow.d: Update
accordingly.
* testsuite/ld-mips-elf/unaligned-branch-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-mips16.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-micromips.d: New test.
* testsuite/ld-mips-elf/unaligned-jump-mips16.d: New test.
* testsuite/ld-mips-elf/unaligned-jump-micromips.d: New test.
* testsuite/ld-mips-elf/unaligned-jump.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-07-19 20:59:28 +08:00
|
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|
|
2016-07-19 Maciej W. Rozycki <macro@imgtec.com>
|
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* config/tc-mips.c (mips_force_relocation): Also retain branch
|
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|
|
|
|
relocations against MIPS16 and microMIPS symbols.
|
|
|
|
|
|
(fix_bad_cross_mode_jump_p): New function.
|
|
|
|
|
|
(fix_bad_same_mode_jalx_p): Likewise.
|
|
|
|
|
|
(fix_bad_misaligned_jump_p): Likewise.
|
|
|
|
|
|
(fix_bad_cross_mode_branch_p): Likewise.
|
|
|
|
|
|
(fix_bad_misaligned_branch_p): Likewise.
|
|
|
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|
(fix_validate_branch): Likewise.
|
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|
(md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP>
|
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|
<BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5,
|
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|
etc. Verify the ISA mode and alignment of the jump target.
|
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<BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check
|
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|
with a call to `fix_validate_branch'.
|
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<BFD_RELOC_MIPS_26_PCREL_S2>: Likewise.
|
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<BFD_RELOC_16_PCREL_S2>: Likewise.
|
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|
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
|
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<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend.
|
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Verify the ISA mode and alignment of the branch target.
|
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(md_convert_frag): Verify the ISA mode and alignment of resolved
|
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MIPS16 branch targets.
|
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* testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction
|
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|
branch targets with `.insn'.
|
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* testsuite/gas/mips/branch-misc-5.s: Likewise.
|
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* testsuite/gas/mips/micromips@branch-misc-5-64.d: Update
|
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accordingly.
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* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
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* testsuite/gas/mips/micromips-branch-relax.s: Annotate
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non-instruction branch target with `.insn'.
|
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* testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets
|
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with external symbols.
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* testsuite/gas/mips/micromips-insn32.d: Update accordingly.
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* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
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* testsuite/gas/mips/micromips-trap.d: Likewise.
|
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* testsuite/gas/mips/micromips.d: Likewise.
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* testsuite/gas/mips/mips16.s: Annotate non-instruction branch
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targets with `.insn'.
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* testsuite/gas/mips/mips16.d: Update accordingly.
|
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* testsuite/gas/mips/mips16-64.d: Likewise.
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* testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction
|
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branch target with `.insn'.
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* testsuite/gas/mips/relax-swap3.s: Likewise.
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* testsuite/gas/mips/branch-local-2.l: New list test.
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* testsuite/gas/mips/branch-local-3.l: New list test.
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* testsuite/gas/mips/branch-local-n32-2.l: New list test.
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* testsuite/gas/mips/branch-local-n32-3.l: New list test.
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* testsuite/gas/mips/branch-local-n64-2.l: New list test.
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* testsuite/gas/mips/branch-local-n64-3.l: New list test.
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* testsuite/gas/mips/unaligned-jump-1.l: New list test.
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* testsuite/gas/mips/unaligned-jump-2.l: New list test.
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* testsuite/gas/mips/unaligned-jump-3.d: New test.
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* testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test.
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* testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test.
|
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* testsuite/gas/mips/unaligned-jump-mips16-3.d: New test.
|
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* testsuite/gas/mips/unaligned-jump-micromips-1.l: New list
|
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|
|
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test.
|
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* testsuite/gas/mips/unaligned-jump-micromips-2.l: New list
|
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|
|
test.
|
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|
* testsuite/gas/mips/unaligned-jump-micromips-3.d: New test.
|
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* testsuite/gas/mips/unaligned-branch-1.l: New list test.
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* testsuite/gas/mips/unaligned-branch-2.l: New list test.
|
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* testsuite/gas/mips/unaligned-branch-3.d: New test.
|
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* testsuite/gas/mips/unaligned-branch-r6-1.l: New list test.
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* testsuite/gas/mips/unaligned-branch-r6-2.l: New list test.
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* testsuite/gas/mips/unaligned-branch-r6-3.l: New list test.
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* testsuite/gas/mips/unaligned-branch-r6-4.l: New list test.
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* testsuite/gas/mips/unaligned-branch-r6-5.d: New test.
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* testsuite/gas/mips/unaligned-branch-r6-6.d: New test.
|
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* testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test.
|
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* testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test.
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* testsuite/gas/mips/unaligned-branch-mips16-3.d: New test.
|
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* testsuite/gas/mips/unaligned-branch-micromips-1.l: New list
|
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test.
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* testsuite/gas/mips/unaligned-branch-micromips-2.l: New list
|
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test.
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* testsuite/gas/mips/unaligned-branch-micromips-3.d: New test.
|
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* testsuite/gas/mips/branch-local-2.s: New test source.
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* testsuite/gas/mips/branch-local-3.s: New test source.
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* testsuite/gas/mips/branch-local-n32-2.s: New test source.
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* testsuite/gas/mips/branch-local-n32-3.s: New test source.
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* testsuite/gas/mips/branch-local-n64-2.s: New test source.
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* testsuite/gas/mips/branch-local-n64-3.s: New test source.
|
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* testsuite/gas/mips/unaligned-jump-1.s: New test source.
|
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* testsuite/gas/mips/unaligned-jump-2.s: New test source.
|
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* testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source.
|
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* testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source.
|
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* testsuite/gas/mips/unaligned-jump-micromips-1.s: New test
|
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|
|
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source.
|
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* testsuite/gas/mips/unaligned-jump-micromips-2.s: New test
|
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|
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source.
|
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* testsuite/gas/mips/unaligned-branch-1.s: New test source.
|
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* testsuite/gas/mips/unaligned-branch-2.s: New test source.
|
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* testsuite/gas/mips/unaligned-branch-r6-1.s: New test source.
|
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* testsuite/gas/mips/unaligned-branch-r6-2.s: New test source.
|
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* testsuite/gas/mips/unaligned-branch-r6-3.s: New test source.
|
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* testsuite/gas/mips/unaligned-branch-r6-4.s: New test source.
|
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|
* testsuite/gas/mips/unaligned-branch-mips16-1.s: New test
|
|
|
|
|
|
source.
|
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|
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|
* testsuite/gas/mips/unaligned-branch-mips16-2.s: New test
|
|
|
|
|
|
source.
|
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|
|
|
* testsuite/gas/mips/unaligned-branch-micromips-1.s: New test
|
|
|
|
|
|
source.
|
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|
|
|
* testsuite/gas/mips/unaligned-branch-micromips-2.s: New test
|
|
|
|
|
|
source.
|
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|
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|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
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|
|
|
|
|
2016-05-21 16:39:05 +08:00
|
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|
|
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
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* config/tc-nds32.c (struct nds32_pseudo_opcode): Make pseudo_val
|
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|
unsigned int.
|
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(do_pseudo_b): Adjust.
|
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(do_pseudo_bal): Likewise.
|
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(do_pseudo_bge): Likewise.
|
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(do_pseudo_bges): Likewise.
|
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(do_pseudo_bgt): Likewise.
|
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(do_pseudo_bgts): Likewise.
|
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(do_pseudo_ble): Likewise.
|
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(do_pseudo_bles): Likewise.
|
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(do_pseudo_blt): Likewise.
|
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(do_pseudo_blts): Likewise.
|
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(do_pseudo_br): Likewise.
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(do_pseudo_bral): Likewise.
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(do_pseudo_la): Likewise.
|
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(do_pseudo_li): Likewise.
|
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(do_pseudo_ls_bhw): Likewise.
|
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|
(do_pseudo_ls_bhwp): Likewise.
|
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|
(do_pseudo_ls_bhwpc): Likewise.
|
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|
(do_pseudo_ls_bhwi): Likewise.
|
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(do_pseudo_move): Likewise.
|
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|
(do_pseudo_neg): Likewise.
|
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|
(do_pseudo_not): Likewise.
|
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|
(do_pseudo_pushpopm): Likewise.
|
|
|
|
|
|
(do_pseudo_pushpop): Likewise.
|
|
|
|
|
|
(do_pseudo_v3push): Likewise.
|
|
|
|
|
|
(do_pseudo_v3pop): Likewise.
|
|
|
|
|
|
(do_pseudo_pushpop_stack): Likewise.
|
|
|
|
|
|
(do_pseudo_push_bhwd): Likewise.
|
|
|
|
|
|
(do_pseudo_pop_bhwd): Likewise.
|
|
|
|
|
|
(do_pseudo_pusha): Likewise.
|
|
|
|
|
|
(do_pseudo_pushi): Likewise.
|
|
|
|
|
|
|
2016-06-27 19:38:33 +08:00
|
|
|
|
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (struct pop_entry): Make the type of reloc
|
|
|
|
|
|
bfd_reloc_code_real_type.
|
|
|
|
|
|
|
2016-06-27 19:38:14 +08:00
|
|
|
|
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (pop_table): Remove sentinel.
|
|
|
|
|
|
(NUM_PERC_ENTRIES): Use ARRAY_SIZE on pop_table.
|
|
|
|
|
|
(md_begin): Adjust.
|
|
|
|
|
|
|
2016-07-18 16:07:26 +08:00
|
|
|
|
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-z8k.c (newfix): Make type of type argument
|
|
|
|
|
|
bfd_reloc_code_real_type.
|
|
|
|
|
|
(apply_fix): Likewise.
|
|
|
|
|
|
|
2016-07-16 11:57:30 +08:00
|
|
|
|
2016-07-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-epiphany.c: Don't include libbfd.h.
|
|
|
|
|
|
* config/tc-frv.c: Likewise.
|
|
|
|
|
|
* config/tc-ip2k.c: Likewise.
|
|
|
|
|
|
* config/tc-iq2000.c: Likewise.
|
|
|
|
|
|
* config/tc-m32c.c: Likewise.
|
|
|
|
|
|
* config/tc-mep.c: Likewise.
|
|
|
|
|
|
* config/tc-mt.c: Likewise.
|
|
|
|
|
|
* config/tc-nios2.c: Likewise.
|
|
|
|
|
|
|
2016-07-16 11:55:11 +08:00
|
|
|
|
2016-07-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/bfin-parse.y: Don't include libbfd.h.
|
|
|
|
|
|
* config/tc-bfin.c: Likewise.
|
|
|
|
|
|
* config/tc-rl78.c: Likewise.
|
|
|
|
|
|
* config/tc-rx.c: Likewise.
|
|
|
|
|
|
* config/tc-metag.c: Likewise.
|
|
|
|
|
|
(create_dspreg_htabs, create_scond_htab): Use gas_assert not BFD_ASSERT.
|
|
|
|
|
|
* Makefile.am: Update dependencies.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
|
MIPS/GAS: Don't convert PC-relative REL relocs against absolute symbols
Don't convert PC-relative REL relocations against absolute symbols to
section-relative references and retain the original symbol reference
instead. Offsets into the absolute section may overflow the limited
range of their in-place addend field, causing an assembly error, e.g.:
$ cat test.s
.text
.globl foo
.ent foo
foo:
b bar
.end foo
.set bar, 0x12345678
$ as -EB -32 -o test.o test.s
test.s: Assembler messages:
test.s:3: Error: relocation overflow
$
With the original reference retained the source can now be assembled and
linked successfully:
$ as -EB -32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000ffff b 0 <foo>
0: R_MIPS_PC16 bar
4: 00000000 nop
...
$ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o
$ objdump -dr test
test: file format elf32-tradbigmips
Disassembly of section .text:
12340000 <foo>:
12340000: 1000159d b 12345678 <bar>
12340004: 00000000 nop
...
$
For simplicity always retain the original symbol reference, even if it
would indeed fit.
Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes
R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch
relocations against absolute symbols to be converted on RELA targets to
section-relative references. This is an intended effect of this change.
Absolute symbols carry no ISA annotation in their `st_other' field and
their value is not going to change with linker relaxation, so it is safe
to discard the original reference and keep the calculated final symbol
value only in the relocation's addend.
Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring
absolute symbols can be safely converted even on REL targets, as there
the in-place addend of these relocations covers the entire 32-bit
address space so it can hold the calculated final symbol value, and
likewise the value referred won't be affected by any linker relaxation.
Add a set of suitable test cases and enable REL linker tests which now
work and were previously used as dump patterns for RELA tests only.
gas/
* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
(mips_force_relocation_abs): New prototype.
* config/tc-mips.c (mips_force_relocation_abs): New function.
* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/branch-absolute-addend.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips-elf.exp: Run
`branch-absolute-addend', `mips16-branch-absolute',
`mips16-branch-absolute-addend' and
`micromips-branch-absolute-addend'.
2016-07-12 08:31:29 +08:00
|
|
|
|
2016-07-14 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
|
|
|
|
|
|
(mips_force_relocation_abs): New prototype.
|
|
|
|
|
|
* config/tc-mips.c (mips_force_relocation_abs): New function.
|
|
|
|
|
|
* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-absolute-addend.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
|
|
|
|
|
|
test.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
MIPS/GAS: Keep the ISA bit in the addend of branch relocations
Correct a problem with the ISA bit being stripped from the addend of
compressed branch relocations, affecting RELA targets. It has been
there since microMIPS support has been added, with:
commit df58fc944dbc6d5efd8d3826241b64b6af22f447
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Sun Jul 24 14:20:15 2011 +0000
<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and
R_MICROMIPS_PC16_S1 relocations originally affected, and the
R_MIPS16_PC16_S1 relocation recently added with commit c9775dde3277
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually
triggering a linker error, due to its heightened processing strictness
level:
$ cat test.s
.text
.set mips16
foo:
b bar
.set bar, 0x1235
.align 4, 0
$ as -EB -n32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1230
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o
test.o: In function `foo':
(.text+0x0): Branch to a non-instruction-aligned address
$
This is because the ISA bit of the branch target does not match the ISA
bit of the referring branch, hardwired to 1 of course.
Retain the ISA bit then, so that the linker knows this is really MIPS16
code referred:
$ objdump -dr fixed.o
fixed.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1231
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o
$
Add a set of MIPS16 tests to cover the relevant cases, excluding linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
gas/
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
addend calculated.
* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
in `bar', export `foo'.
* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
accordingly.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
Likewise.
ld/
* testsuite/ld-mips-elf/mips16-branch-absolute.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `mips16-branch-absolute' and
`mips16-branch-absolute-addend', referred indirectly only.
2016-07-12 08:30:48 +08:00
|
|
|
|
2016-07-14 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
|
|
|
|
|
|
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
|
|
|
|
|
|
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
|
|
|
|
|
|
addend calculated.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
|
|
|
|
|
|
in `bar', export `foo'.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
|
|
|
|
|
|
accordingly.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
|
|
|
|
|
|
Likewise.
|
|
|
|
|
|
|
BFD: Let targets handle relocations against absolute symbols
Fix a generic BFD issue with relocations against absolute symbols, which
are installed without using any individual relocation handler provided
by the backend. This causes any absolute section's addend to be lost on
REL targets such as o32 MIPS, and also relocation-specific calculation
adjustments are not made.
As an example assembling this program:
$ cat test.s
.text
foo:
b bar
b baz
.set bar, 0x1234
$ as -EB -32 -o test-o32.o test.s
$ as -EB -n32 -o test-n32.o test.s
produces this binary code:
$ objdump -dr test-o32.o test-n32.o
test-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
test-n32.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 10000000 b 4 <foo+0x4>
0: R_MIPS_PC16 *ABS*+0x1230
4: 00000000 nop
8: 10000000 b c <foo+0xc>
8: R_MIPS_PC16 baz-0x4
c: 00000000 nop
$
where it is clearly visible in `test-o32.o', which uses REL relocations,
that the absolute section's addend equivalent to the value of `bar' -- a
reference to which cannot be fully resolved at the assembly time,
because the reference is PC-relative -- has been lost, as has been the
relocation-specific adjustment of -4, required to take into account the
PC+4-relative calculation made by hardware with branches and seen in the
external symbol reference to `baz' as the `ffff' addend encoded in the
instruction word. In `test-n32.o', which uses RELA relocations, the
absolute section's addend has been correctly retained.
Give precedence then in `bfd_perform_relocation' and
`bfd_install_relocation' to any individual relocation handler the
backend selected may have provided, while still resorting to the generic
calculation otherwise. This retains the semantics which we've had since
forever or before the beginning of our repository history, and is at the
very least compatible with `bfd_elf_generic_reloc' being used as the
handler.
Retain the `bfd_is_und_section' check unchanged at the beginning of
`bfd_perform_relocation' since this does not affect the semantics of the
function. The check returns the same `bfd_reloc_undefined' code the
check for a null `howto' does, so swapping the two does not matter.
Also the check is is mutually exclusive with the `bfd_is_abs_section'
check, since a section cannot be absolute and undefined both at once, so
swapping the two does not matter either.
With this change applied the program quoted above now has the in-place
addend correctly calculated and installed in the field being relocated:
$ objdump -dr fixed-o32.o
fixed-o32.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000048c b 1234 <bar>
0: R_MIPS_PC16 *ABS*
4: 00000000 nop
8: 1000ffff b 8 <foo+0x8>
8: R_MIPS_PC16 baz
c: 00000000 nop
$
Add a set of MIPS tests to cover the relevant cases, including absolute
symbols with addends, and verifying that PC-relative relocations against
symbols concerned resolve to the same value in the final link regardless
of whether the REL or the RELA relocation form is used. Exclude linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
bfd/
* reloc.c (bfd_perform_relocation): Try the `howto' handler
first with relocations against absolute symbols.
(bfd_install_relocation): Likewise.
gas/
* testsuite/gas/mips/mips16-branch-absolute.d: Update patterns.
* testsuite/gas/mips/branch-absolute.d: New test.
* testsuite/gas/mips/branch-absolute-n32.d: New test.
* testsuite/gas/mips/branch-absolute-n64.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n32.d: New test.
* testsuite/gas/mips/branch-absolute-addend-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New
test.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New
test.
* testsuite/gas/mips/branch-absolute.s: New test source.
* testsuite/gas/mips/branch-absolute-addend.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute-addend.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute.s: New test
source.
* testsuite/gas/mips/micromips-branch-absolute-addend.s: New
test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/branch-absolute.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n32.d: New test.
* testsuite/ld-mips-elf/branch-absolute-addend-n64.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute.d: New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d:
New test.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d:
New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `branch-absolute-addend' and
`micromips-branch-absolute-addend', referred indirectly only.
2016-07-12 08:30:01 +08:00
|
|
|
|
2016-07-14 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute.d: Update patterns.
|
|
|
|
|
|
* testsuite/gas/mips/branch-absolute.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-absolute-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-absolute-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-absolute-addend-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-absolute-addend-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New
|
|
|
|
|
|
test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New
|
|
|
|
|
|
test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New
|
|
|
|
|
|
test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New
|
|
|
|
|
|
test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-absolute.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/branch-absolute-addend.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute-addend.s: New test
|
|
|
|
|
|
source.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute.s: New test
|
|
|
|
|
|
source.
|
|
|
|
|
|
* testsuite/gas/mips/micromips-branch-absolute-addend.s: New
|
|
|
|
|
|
test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
MIPS/opcodes: Address issues with NAL disassembly
Address issues with the disassembly of the NAL assembly idiom and R6
instruction introduced with commit 7361da2c952e ("Add support for MIPS
R6.") and then further tweaked with commit b9121b573e2e ("Add in a JALRC
alias and fix the NAL instruction."). As from R6 this instruction has
replaced the encoding of `bltzal $0, . + 4' as the solely supported form
of the former BLTZAL instruction for the regular MIPS ISA.
The instruction is marked as an alias only in our regular MIPS opcode
table, making it fail to disassemble in R6 code if the `no-aliases'
machine option has been passed to `objdump':
$ cat test.s
.text
foo:
nal
$ as -mips64r6 -o test.o test.s
$ objdump -dr --prefix-addresses --show-raw-insn -M no-aliases test.o
nal.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo> 04100000 0x4100000
...
$
This is because the `bltzal' entry has been marked as pre-R6 only in the
opcode table and there is no other opcode pattern to match.
Additionally the changes referred made NAL replace the equivalent
`bltzal $0, . + 4' instruction in disassembly, unless the `no-aliases'
machine option has been used, in legacy code. Seeing NAL, especially in
its updated form lacking the branch target argument, in the disassembly
of such code may be confusing to people. This is because unlike with
EHB only used in R2 and newer code -- the machine encoding of which we
anyway always disassemble to its corresponding current architecture's
mnemonic rather than its legacy meaning of `sll $0, $0, 3' -- BLTZAL has
been indeed used in legacy code. Even though `bltzal $0, . + 8' and its
machine code encoding (0x04100001) -- which is not equivalent to NAL and
still disassembles as BLTZAL -- has been the predominant form as opposed
to NAL's `bltzal $0, . + 4' (0x04100000), it makes sense to always keep
the old form in disassembly, while still accepting `nal' in assembly.
Remove the alias marking then from the the `nal' instruction pattern,
making it always match for R6 code, even with the `no-aliases' option.
And move the entry beyond the `bltzal' entry, making the latter one take
precedence for legacy binary code, while letting the former still match
any `nal' mnemonic in source code assembled for a legacy target.
Add a suitable test case to the GAS test suite. While the change
affects the disassembler more than the assembler, so placing the test
case in the binutils test suite might be more appropriate, the intent is
also to verify that `nal' is still accepted by GAS for legacy targets,
plus we have test infrastructure available in the GAS test suite for
automatic multiple ISA level testing, which we lack from the binutils
framework.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
annotation from the "nal" entry and reorder it beyond "bltzal".
gas/
* testsuite/gas/mips/nal-1.d: New test.
* testsuite/gas/mips/mipsr6@nal-1.d: New test.
* testsuite/gas/mips/nal-2.d: New test.
* testsuite/gas/mips/mipsr6@nal-2.d: New test.
* testsuite/gas/mips/nal.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-07-08 23:07:39 +08:00
|
|
|
|
2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/nal-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@nal-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/nal-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@nal-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/nal.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-07-13 16:42:28 +08:00
|
|
|
|
2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/sparc/ldtxa.s: New file.
|
|
|
|
|
|
* testsuite/gas/sparc/ldtxa.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/sparc.exp: Execute the ldtxa test.
|
|
|
|
|
|
|
2016-06-30 21:11:57 +08:00
|
|
|
|
2016-07-11 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (arc_reloc_op_tag): Allow complex ops for dtpoff.
|
|
|
|
|
|
(tc_gen_reloc): Remove passing DTPOFF base info into reloc addendum
|
|
|
|
|
|
as it is no longer needed.
|
|
|
|
|
|
|
2016-07-14 00:31:17 +08:00
|
|
|
|
2016-07-08 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (append_insn): Remove extraneous
|
|
|
|
|
|
`install_insn' call.
|
|
|
|
|
|
|
2016-07-05 17:14:51 +08:00
|
|
|
|
2016-07-04 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (check_qword_reg): Correct register kind
|
|
|
|
|
|
checked.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-suffix-bad.s: Add q-suffix with
|
|
|
|
|
|
16-bit register cases.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-suffix-bad.l: Adjust expectations.
|
|
|
|
|
|
|
|
|
|
|
|
|
2016-07-03 06:39:18 +08:00
|
|
|
|
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/ecoff@ld.d: Remove test.
|
|
|
|
|
|
* testsuite/gas/mips/ecoff@ld-forward.d: Remove test.
|
|
|
|
|
|
* testsuite/gas/mips/ecoff@ld-zero-3.d: Remove test.
|
|
|
|
|
|
* testsuite/gas/mips/ecoff@sd.d: Remove test.
|
|
|
|
|
|
* testsuite/gas/mips/ecoff@sd-forward.d: Remove test.
|
|
|
|
|
|
* testsuite/gas/mips/beq.d: Remove a.out and ECOFF support from
|
|
|
|
|
|
reloc patterns.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@beq.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/bge.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@bge.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/bgeu.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@bgeu.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/blt.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@blt.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/bltu.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@bltu.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-likely.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/la.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/lb.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/lifloat.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/sb.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/uld.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/ulh.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/ulw.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/usd.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/ush.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/usw.d: Likewise.
|
|
|
|
|
|
|
2016-07-03 06:09:06 +08:00
|
|
|
|
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-2.s: Move non
|
|
|
|
|
|
locally-defined-global symbol tests...
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-5.s: ... to this new test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-2.d: Update accordingly.
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-2-64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-2pic.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-2pic-64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@branch-misc-2-64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@branch-misc-2pic-64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-2-64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-2pic.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-5.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-5pic.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-5-64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-misc-5pic-64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@branch-misc-5-64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@branch-misc-5pic-64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-5.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-5pic.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-5-64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-07-03 05:19:15 +08:00
|
|
|
|
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/beq.s: Uncomment branches to undefined
|
|
|
|
|
|
symbols.
|
|
|
|
|
|
* testsuite/gas/mips/beq.d: Update accordingly.
|
|
|
|
|
|
* testsuite/gas/mips/mipsr6@beq.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@beq.d: Likewise.
|
|
|
|
|
|
|
2016-07-03 05:14:27 +08:00
|
|
|
|
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Restrict 64-bit `branch-mips'
|
|
|
|
|
|
tests to NewABI targets.
|
|
|
|
|
|
|
2016-07-03 05:04:41 +08:00
|
|
|
|
2016-07-02 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Group `branch-misc' tests
|
|
|
|
|
|
together.
|
|
|
|
|
|
|
2016-07-01 23:20:50 +08:00
|
|
|
|
2016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add
|
|
|
|
|
|
require field.
|
|
|
|
|
|
(aarch64_features): Initialize require fields.
|
|
|
|
|
|
(aarch64_parse_features): Handle dependencies.
|
|
|
|
|
|
(aarch64_feature_enable_set, aarch64_feature_disable_set): New.
|
|
|
|
|
|
(md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES.
|
|
|
|
|
|
* testsuite/gas/aarch64/illegal-nofp16.s: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/illegal-nofp16.l: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/illegal-nofp16.d: New.
|
|
|
|
|
|
|
2016-07-01 19:35:01 +08:00
|
|
|
|
2016-07-01 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* macro.c (macro_expand_body): Use a buffer big enough to hold an
|
|
|
|
|
|
extremely large integer.
|
|
|
|
|
|
|
2016-07-01 17:17:30 +08:00
|
|
|
|
2016-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/mpx-inval-2.l: Relax for COFF targets.
|
|
|
|
|
|
|
2016-07-01 16:57:46 +08:00
|
|
|
|
2016-07-01 Tristan Gingold <gingold@adacore.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Add marker for 2.27.
|
|
|
|
|
|
|
2016-07-01 15:07:15 +08:00
|
|
|
|
2016-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tc-i386.c (i386_index_check): Add special checks for bndmk,
|
|
|
|
|
|
bndldx, and bndstx.
|
|
|
|
|
|
* testsuite/gas/i386/mpx-inval-2.s: Add %rip and %eip relative
|
|
|
|
|
|
as well as scaling by other than 1 tests.
|
|
|
|
|
|
* testsuite/gas/i386/mpx-inval-2.l: Adjust accordingly.
|
|
|
|
|
|
|
2016-07-01 15:06:16 +08:00
|
|
|
|
2016-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* tc-i386.c (md_assemble): Alter address size checking for MPX
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
* testsuite/gas/i386/mpx-inval-2.s: New.
|
|
|
|
|
|
* testsuite/gas/i386/mpx-inval-2.l: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test.
|
|
|
|
|
|
|
x86/Intel: don't accept bogus instructions
... due to their last byte looking like a suffix, when after its
stripping a matching instruction can be found. Since memory operand
size specifiers in Intel mode get converted into suffix representation
internally, we need to keep track of the actual mnemonic suffix which
may have got trimmed off, and check its validity while looking for a
matching template. I tripper over this quite some time again after
support for AMD's SSE5 instructions got removed, as at that point some
of the SSE5 mnemonics, other than expected, didn't fail to assemble.
But the problem affects many more instructions, namely (almost) all
MMX, SSE, and AVX ones as it looks. I don't think it makes sense to
add a testcase covering all of them, nor do I think it makes sense to
pick out some random examples for a new test case.
2016-07-01 15:03:02 +08:00
|
|
|
|
2016-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20318
|
|
|
|
|
|
* config/tc-i386.c (match_template): Add char parameter,
|
|
|
|
|
|
consumed in Intel mode for an extra suffix check.
|
|
|
|
|
|
(md_assemble): New local variable mnem_suffix.
|
|
|
|
|
|
* testsuite/gas/i386/suffix-bad.s: New.
|
|
|
|
|
|
* testsuite/gas/i386/suffix-bad.l: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new test (twice).
|
|
|
|
|
|
|
2016-07-01 15:01:41 +08:00
|
|
|
|
2016-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/movz.s: New.
|
|
|
|
|
|
* testsuite/gas/i386/movz32.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/movz64.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
|
2016-07-01 14:56:13 +08:00
|
|
|
|
2016-07-01 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (struct _i386_insn): New field memop1_string.
|
|
|
|
|
|
(md_assemble): Free first memory operand string.
|
|
|
|
|
|
(i386_index_check): Use repprefixok to distingush xlat from
|
|
|
|
|
|
other (real) string ops.
|
|
|
|
|
|
(maybe_adjust_templates): New.
|
|
|
|
|
|
(i386_att_operand). Call it. Store first memory operand string.
|
|
|
|
|
|
* config/tc-i386-intel.c (i386_intel_operand): Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/intel-movs.s: New.
|
|
|
|
|
|
* testsuite/gas/i386/intel-movs32.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/intel-movs64.d: New.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests. Invoke as for
|
|
|
|
|
|
64-bits tests with "--defsym x86_64=1 --strip-local-absolute".
|
|
|
|
|
|
|
2016-07-01 04:49:54 +08:00
|
|
|
|
2016-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (get_append_method): Fix a comment typo.
|
|
|
|
|
|
|
MIPS16/GAS: Fix delay slot filling across frags
Fix an assertion failure like:
test.s: Assembler messages:
test.s:3: Internal error!
Assertion failure in append_insn at .../gas/config/tc-mips.c:7523.
Please report this bug.
triggered by assembling MIPS16 code like:
hello:
addiu $4, $4, 4
jr $31
with the generation of a listing file enabled, e.g.:
$ as -mips16 -O2 -aln=test.lst
The cause of the problem is the lack of support for moving instructions
across frags in MIPS16 jump swapping, which triggers more easily with
listing enabled as in that case every instruction gets placed in its own
frag. It would trigger even with listing disabled though if the
instruction to swap a MIPS16 jump with was unfortunately enough placed
as last in a frag that became full.
This scenario is already handled correctly with branch swapping in
regular MIPS and microMIPS code, so reuse it for MIPS16 code as well,
and now that all MIPS16 handling has become the same as the regular MIPS
and microMIPS cases remove MIPS16 special casing altogether.
This effectively complements:
commit 464ab0e55ade01d2bb0b4fa45c429af7a2f85a26
Author: Maciej W. Rozycki <macro@linux-mips.org>
Date: Mon Aug 6 20:33:00 2012 +0000
<https://sourceware.org/ml/binutils/2012-08/msg00043.html>, ("MIPS/GAS:
Correct microMIPS branch swapping assertion") for the MIPS16 case.
The assertion itself was introduced with:
commit 1e91584932efd70020c8c98037d0cb93a0552a20
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), but its introduction
merely noted our existing lack of support for MIPS16 jump swapping
across frags.
gas/
* config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special
case MIPS16 handling.
* testsuite/gas/mips/branch-swap-3.d: New test.
* testsuite/gas/mips/branch-swap-4.d: New test.
* testsuite/gas/mips/mips16@branch-swap-3.d: New test.
* testsuite/gas/mips/mips16@branch-swap-4.d: New test.
* testsuite/gas/mips/micromips@branch-swap-3.d: New test.
* testsuite/gas/mips/micromips@branch-swap-4.d: New test.
* testsuite/gas/mips/branch-swap-3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-30 22:02:20 +08:00
|
|
|
|
2016-06-30 Matthew Fortune <Matthew.Fortune@imgtec.com>
|
|
|
|
|
|
Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special
|
|
|
|
|
|
case MIPS16 handling.
|
|
|
|
|
|
* testsuite/gas/mips/branch-swap-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-swap-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16@branch-swap-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16@branch-swap-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-swap-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-swap-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-swap-3.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
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|
|
|
|
2016-06-30 19:46:47 +08:00
|
|
|
|
2016-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (append_insn): Simplify non-MIPS16 branch
|
|
|
|
|
|
swapping sequence.
|
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|
PR gas/20312: Do not pad sections to alignment on failed assembly
Correct a regression from commit 85024cd8bcb9 ("Run write_object_file
after errors") causing unsuccessful assembly, which may be due to any
reason, such as supplying a valid source like this:
.text
.byte 0
.err
to terminate with an assertion failure like:
test.s: Assembler messages:
test.s:3: Error: .err encountered
../as-new: BFD (GNU Binutils) 2.24.51.20140628 internal error, aborting at .../gas/write.c line 608 in size_seg
../as-new: Please report this bug.
on targets whose default text section alignment is above 0, typically
RISC machines.
This is due to an attempt to set last text section's frag alignment to
0, requested from `subsegs_finish_section' where `frag_align_code
(alignment, 0)' is called with `alignment' set to 0 rather than the
section alignment if `had_errors' has returned true. The call to
`subsegs_finish_section' is made from `subsegs_finish' from
`write_object_file' at unsuccessful completion, which previously wasn't
made.
Always set last section's frag alignment from the section alignment
then, forcing no section padding instead if completing unsuccessfully,
so that in that case alignment padding is still suppressed from any
listing generated, fixing assertion failures for these targets:
alpha-linuxecoff -FAIL: all pr20312
arm-aout -FAIL: all pr20312
mips-freebsd -FAIL: all pr20312
mips-img-linux -FAIL: all pr20312
mips-linux -FAIL: all pr20312
mips-mti-linux -FAIL: all pr20312
mips-netbsd -FAIL: all pr20312
mips-sgi-irix5 -FAIL: all pr20312
mips-sgi-irix6 -FAIL: all pr20312
mips-vxworks -FAIL: all pr20312
mips64-freebsd -FAIL: all pr20312
mips64-img-linux -FAIL: all pr20312
mips64-linux -FAIL: all pr20312
mips64-mti-linux -FAIL: all pr20312
mips64-openbsd -FAIL: all pr20312
mips64el-freebsd -FAIL: all pr20312
mips64el-img-linux -FAIL: all pr20312
mips64el-linux -FAIL: all pr20312
mips64el-mti-linux -FAIL: all pr20312
mips64el-openbsd -FAIL: all pr20312
mipsel-freebsd -FAIL: all pr20312
mipsel-img-linux -FAIL: all pr20312
mipsel-linux -FAIL: all pr20312
mipsel-mti-linux -FAIL: all pr20312
mipsel-netbsd -FAIL: all pr20312
mipsel-vxworks -FAIL: all pr20312
mipsisa32-linux -FAIL: all pr20312
mipsisa32el-linux -FAIL: all pr20312
mipsisa64-linux -FAIL: all pr20312
mipsisa64el-linux -FAIL: all pr20312
sh-pe -FAIL: all pr20312
sparc-aout -FAIL: all pr20312
gas/
PR gas/20312
* write.c (subsegs_finish_section): Force no section padding to
alignment on failed assembly, always set last frag's alignment
from section.
* testsuite/gas/all/pr20312.l: New list test.
* testsuite/gas/all/pr20312.s: New test source.
* testsuite/gas/all/gas.exp: Run the new test
2016-06-29 08:38:50 +08:00
|
|
|
|
2016-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
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|
|
|
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|
|
PR gas/20312
|
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|
|
|
|
* write.c (subsegs_finish_section): Force no section padding to
|
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|
|
|
|
alignment on failed assembly, always set last frag's alignment
|
|
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|
|
|
from section.
|
|
|
|
|
|
* testsuite/gas/all/pr20312.l: New list test.
|
|
|
|
|
|
* testsuite/gas/all/pr20312.s: New test source.
|
|
|
|
|
|
* testsuite/gas/all/gas.exp: Run the new test
|
|
|
|
|
|
|
2016-06-30 23:53:20 +08:00
|
|
|
|
2016-06-30 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
|
|
|
|
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|
|
* config.in (TARGET_WITH_CPU): Undefine.
|
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|
|
|
|
* configure.ac: Add --with-cpu support, and define in config.h.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* config/tc-arc.c: Use TARGET_WITH_CPU to select default CPU.
|
|
|
|
|
|
* NEWS: Mention new configure option.
|
|
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|
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|
|
2016-06-30 17:46:51 +08:00
|
|
|
|
2016-06-30 Matthew Wahab <matthew.wahab@arm.com>
|
|
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|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/armv8_2+rdma.d: New.
|
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|
|
2016-06-30 00:29:39 +08:00
|
|
|
|
2016-06-29 H.J. Lu <hongjiu.lu@intel.com>
|
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|
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|
|
* NEWS: Mention --enable-compressed-debug-sections=gas is the
|
|
|
|
|
|
default for Linux/x86 targets.
|
|
|
|
|
|
* configure.tgt (ac_default_compressed_debug_sections): Default
|
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|
|
to yes for Linux/x86 targets.
|
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|
2016-06-29 00:33:38 +08:00
|
|
|
|
2016-06-29 Maciej W. Rozycki <macro@imgtec.com>
|
|
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|
* write.c: Remove "libbfd.h" inclusion.
|
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|
2016-06-28 20:21:36 +08:00
|
|
|
|
2016-06-28 Maciej W. Rozycki <macro@imgtec.com>
|
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|
|
|
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|
|
* testsuite/gas/elf/elf.exp: Use `supports_gnu_unique' with the
|
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|
`type' test.
|
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|
2016-06-28 17:33:59 +08:00
|
|
|
|
2016-06-28 Alan Modra <amodra@gmail.com>
|
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|
|
PR gas/20247
|
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|
|
|
|
* testsuite/gas/elf/section11.s: Don't start directives in first column.
|
|
|
|
|
|
|
2016-06-28 16:21:04 +08:00
|
|
|
|
2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
|
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|
|
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|
|
* testsuite/gas/aarch64/diagnostic.s,
|
|
|
|
|
|
testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.
|
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|
MIPS16: Add R_MIPS16_PC16_S1 branch relocation support
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1'
and the usual MIPS16 bit shuffling applies to relocated field handling,
as per the encoding of the branch target in the extended form of the
MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions.
include/
* elf/mips.h (R_MIPS16_PC16_S1): New relocation.
bfd/
* elf32-mips.c (elf_mips16_howto_table_rel): Add
R_MIPS16_PC16_S1.
(mips16_reloc_map): Likewise.
* elf64-mips.c (mips16_elf64_howto_table_rel): Likewise.
(mips16_elf64_howto_table_rela): Likewise.
(mips16_reloc_map): Likewise.
* elfn32-mips.c (elf_mips16_howto_table_rel): Likewise.
(elf_mips16_howto_table_rela): Likewise.
(mips16_reloc_map): Likewise.
* elfxx-mips.c (mips16_branch_reloc_p): New function.
(mips16_reloc_p): Handle R_MIPS16_PC16_S1.
(b_reloc_p): Likewise.
(mips_elf_calculate_relocation): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
* reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-mips.c (mips16_reloc_p): Handle
BFD_RELOC_MIPS16_16_PCREL_S1.
(b_reloc_p): Likewise.
(limited_pcrel_reloc_p): Likewise.
(md_pcrel_from): Likewise.
(md_apply_fix): Likewise.
(tc_gen_reloc): Likewise.
(md_convert_frag): Likewise.
(mips_fix_adjustable): Update comment.
* testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-addend-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-addend-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file.
* testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file.
* testsuite/gas/mips/mips16-branch-addend-2.l: Remove file.
* testsuite/gas/mips/mips16-branch-addend-3.l: Remove file.
* testsuite/gas/mips/mips16-branch-absolute.l: Remove file.
* testsuite/gas/mips/mips16-branch-addend-2.s: Add padding.
* testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid
implicit instruction padding, avoid MIPS16 JR->JRC conversion.
* testsuite/gas/mips/branch-weak-6.d: New test.
* testsuite/gas/mips/branch-weak-7.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips16-branch-2.d: New test.
* testsuite/ld-mips-elf/mips16-branch-3.d: New test.
* testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test.
* testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test.
* testsuite/ld-mips-elf/mips16-branch.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-28 08:23:36 +08:00
|
|
|
|
2016-06-28 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips16_reloc_p): Handle
|
|
|
|
|
|
BFD_RELOC_MIPS16_16_PCREL_S1.
|
|
|
|
|
|
(b_reloc_p): Likewise.
|
|
|
|
|
|
(limited_pcrel_reloc_p): Likewise.
|
|
|
|
|
|
(md_pcrel_from): Likewise.
|
|
|
|
|
|
(md_apply_fix): Likewise.
|
|
|
|
|
|
(tc_gen_reloc): Likewise.
|
|
|
|
|
|
(md_convert_frag): Likewise.
|
|
|
|
|
|
(mips_fix_adjustable): Update comment.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error
|
|
|
|
|
|
output, add dump patterns.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error
|
|
|
|
|
|
output, add dump patterns.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-2.d: Remove error
|
|
|
|
|
|
output, add dump patterns.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-3.d: Remove error
|
|
|
|
|
|
output, add dump patterns.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute.d: Remove error
|
|
|
|
|
|
output, add dump patterns.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-2.l: Remove file.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-3.l: Remove file.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute.l: Remove file.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-2.s: Add padding.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid
|
|
|
|
|
|
implicit instruction padding, avoid MIPS16 JR->JRC conversion.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak-6.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak-7.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-06-27 23:50:29 +08:00
|
|
|
|
2016-06-27 Vineet Gupta <vgupta@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config//tc-arc.c (tc_arc_frame_initial_instructions): Use
|
|
|
|
|
|
cfi_add_CFA_def_cfa to generate default CFA with offset
|
|
|
|
|
|
* testsuite/gas/cfi/cfi-arc-1.d: Update expected output.
|
|
|
|
|
|
|
2016-06-27 20:52:20 +08:00
|
|
|
|
2016-06-27 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20247
|
|
|
|
|
|
* as.h (do_not_pad_sections_to_alignment): New global variable.
|
|
|
|
|
|
* as.c (show_usage): Add --no-pad-sections.
|
|
|
|
|
|
(parse_args): Likewise.
|
|
|
|
|
|
* write.c (size_seg): Skip padding the end of the section if
|
|
|
|
|
|
requested from the command line.
|
|
|
|
|
|
(SUB_SEGMENT_ALIGN): Likewise.
|
|
|
|
|
|
* doc/as.texinfo: Document the new option.
|
|
|
|
|
|
* NEWS: Mention the new feature.
|
|
|
|
|
|
* testsuite/gas/elf/section11.s: New test.
|
|
|
|
|
|
* testsuite/gas/elf/section11.d: New test driver.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run the new test.
|
|
|
|
|
|
|
2016-06-27 18:01:34 +08:00
|
|
|
|
2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-dlx.c: Include bfd/elf32-dlx.h.
|
|
|
|
|
|
* config/tc-dlx.h: Remove prototype of dlx_set_skip_hi16.
|
|
|
|
|
|
|
2016-05-23 12:35:40 +08:00
|
|
|
|
2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_elf_suffix): Use ARRAY_SIZE instead of a
|
|
|
|
|
|
sentinal element.
|
|
|
|
|
|
(map_suffix_reloc_to_operator): Likewise.
|
|
|
|
|
|
(map_operator_to_reloc): Likewise.
|
|
|
|
|
|
|
2016-05-29 06:16:47 +08:00
|
|
|
|
2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nds32.c (md_begin): Use ARRAY_SIZE instead of a sentinal
|
|
|
|
|
|
element in relax_table.
|
|
|
|
|
|
|
2016-06-05 05:56:32 +08:00
|
|
|
|
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c: Make the type of reg_entry::type
|
|
|
|
|
|
aarch_reg_type.
|
|
|
|
|
|
|
2016-04-21 21:56:50 +08:00
|
|
|
|
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-bfin.c (bfin_cpus): Remove sentinal.
|
|
|
|
|
|
(md_parse_option): Adjust.
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_parse_abi): Replace use of a sentinal
|
|
|
|
|
|
with iteration from 0 to ARRAY_SIZE.
|
|
|
|
|
|
* config/tc-mcore.c (md_begin): Likewise.
|
|
|
|
|
|
* config/tc-visium.c (visium_parse_arch): Likewise.
|
|
|
|
|
|
|
2016-06-06 10:25:21 +08:00
|
|
|
|
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-tic54x.c (tic54x_set_default_include): remove argument
|
|
|
|
|
|
and simplify accordingly.
|
|
|
|
|
|
(tic54x_include): Adjust.
|
|
|
|
|
|
(tic54x_mlib): Likewise.
|
|
|
|
|
|
|
2016-06-05 04:46:58 +08:00
|
|
|
|
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_make_property_section): Remove prototype.
|
|
|
|
|
|
|
2016-06-25 07:49:10 +08:00
|
|
|
|
2016-06-24 Maciej W. Rozycki <macro@imgtec.com>
|
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|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (append_insn): Use any `O_symbol' expression
|
|
|
|
|
|
unchanged with relaxed MIPS16 instructions.
|
|
|
|
|
|
(mips16_extended_frag): Adjust accordingly. Return 1 right
|
|
|
|
|
|
away if a relocation will be required for the symbol requested.
|
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|
|
|
|
Remove dead first relaxation pass code.
|
|
|
|
|
|
(mips_relax_frag): Pass `sec' down to `mips16_extended_frag'.
|
|
|
|
|
|
(md_convert_frag): Adjust symbol value calculation. Raise an
|
|
|
|
|
|
error if a relocation is required for the symbol requested.
|
|
|
|
|
|
* testsuite/gas/mips/mips16@relax-swap3.d: Remove dump patterns,
|
|
|
|
|
|
add error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16@relax-swap3.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-relax-0.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-relax-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-relax-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-relax-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-0.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-5.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-6.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-7.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-0.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-absolute.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-0.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-0.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-0.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-2.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-3.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-6.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-7.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-2.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-3.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-absolute.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-2.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-3.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-2.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-3.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-2.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-3.l: New error output.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-relax-0.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-relax-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-0.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-3.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-4.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-5.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-6.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-reloc-7.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-0.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-addend-3.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-pcrel-absolute.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-0.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-reloc-3.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-0.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-addend-3.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-branch-absolute.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-0.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips16-absolute-reloc-3.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-06-24 09:24:50 +08:00
|
|
|
|
2016-06-24 Alan Modra <amodra@gmail.com>
|
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|
|
* configure.tgt (alpha-*-openbsd*): Use em=nbsd.
|
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|
|
2016-06-23 18:33:52 +08:00
|
|
|
|
2016-06-23 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (b_reloc_p): New function.
|
|
|
|
|
|
(mips_fix_adjustable): Also keep the original microMIPS symbol
|
|
|
|
|
|
referred from branch relocations.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-n32-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-n64-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Update
|
|
|
|
|
|
relocations.
|
|
|
|
|
|
* testsuite/gas/mips/branch-local-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new cases.
|
|
|
|
|
|
|
[ARC] Misc minor edits/fixes
The code supporting -mspfp, -mdpfp, and -mfpuda options are in
sections of code that are commented as being for backward
compatibility only, and having no effect. However, they do have an
effect, enabling the SPX, DPX, and DPA instruction subclasses
respectively. This commit moves the code supporting these options
away from the comments indicating that they are dummy options, and
also fixes a small issue where -mnps400 had the additional effect
of enabling SPX instructions.
A couple of other minor edits (that make no functional change) are
also included.
gas/ChangeLog:
* config/tc-arc.c (options, md_longopts, md_parse_option):
Move -mspfp, -mdpfp and -mfpuda out of the sections for
dummy options. Correct erroneous enabling of SPFP
instructions when using -mnps400.
include/ChangeLog:
* opcode/arc.h: Make insn_class_t alphabetical again.
opcodes/ChangeLog:
* arc-opc.c: Correct description of availability of NPS400
features.
2016-06-22 03:25:29 +08:00
|
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|
|
2016-06-23 Graham Markall <graham.markall@embecosm.com>
|
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|
|
|
|
|
|
|
|
|
* config/tc-arc.c (options, md_longopts, md_parse_option): Move
|
|
|
|
|
|
-mspfp, -mdpfp and -mfpuda out of the sections for dummy
|
|
|
|
|
|
options. Correct erroneous enabling of SPFP instructions when
|
|
|
|
|
|
using -mnps400.
|
|
|
|
|
|
|
Add support for yet some more new ISA 3.0 instructions.
opcodes/
* ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
(powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
xor3>: New mnemonics.
<setb>: Change to a VX form instruction.
(insert_sh6): Add support for rldixor.
(extract_sh6): Likewise.
gas/
* testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce,
mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor,
setbool, xor3>: New tests.
* testsuite/gas/ppc/power9.s: Likewise.
2016-06-23 06:55:17 +08:00
|
|
|
|
2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
|
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|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce,
|
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|
|
|
|
mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor,
|
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|
|
|
|
setbool, xor3>: New tests.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.s: Likewise.
|
|
|
|
|
|
|
2016-06-05 04:45:13 +08:00
|
|
|
|
2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c: Include elf/xtensa.h.
|
|
|
|
|
|
|
2016-06-22 04:22:39 +08:00
|
|
|
|
2016-06-21 Maciej W. Rozycki <macro@imgtec.com>
|
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|
|
|
|
|
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|
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|
|
* config/tc-mips.c (calculate_reloc) <BFD_RELOC_HI16_S_PCREL>
|
|
|
|
|
|
<BFD_RELOC_LO16_PCREL>: New switch cases.
|
|
|
|
|
|
(md_apply_fix) <BFD_RELOC_HI16_S_PCREL, BFD_RELOC_LO16_PCREL>:
|
|
|
|
|
|
Move switch cases along `BFD_RELOC_MIPS_JMP'.
|
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|
|
|
<BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2>
|
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|
|
|
<BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MIPS_19_PCREL_S2>: Handle
|
|
|
|
|
|
the resolved case.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-4-r6.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-5.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-5-r6.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-6.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-6.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-4.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-6.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-06-22 03:12:00 +08:00
|
|
|
|
2016-06-21 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS_18_PCREL_S3>
|
|
|
|
|
|
<BFD_RELOC_MIPS_19_PCREL_S2>: Avoid null pointer dereferences
|
|
|
|
|
|
via `fixP->fx_addsy'.
|
|
|
|
|
|
|
2016-06-22 01:54:16 +08:00
|
|
|
|
2016-06-21 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_pcrel_from) <BFD_RELOC_MIPS_18_PCREL_S3>:
|
|
|
|
|
|
Calculate relocation from the containing aligned doubleword.
|
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|
|
|
(tc_gen_reloc) <BFD_RELOC_MIPS_18_PCREL_S3>: Calculate the
|
|
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|
|
|
addend from the containing aligned doubleword.
|
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|
|
|
|
|
2016-06-21 23:01:27 +08:00
|
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|
|
2016-06-21 Maciej W. Rozycki <macro@imgtec.com>
|
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|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_force_relocation): Use `file_mips_opts'
|
|
|
|
|
|
rather than `mips_opts' for the R6 ISA check.
|
|
|
|
|
|
(mips_fix_adjustable): Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-1-r6.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-2-r6.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/pcrel-reloc-3-r6.d: New test.
|
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|
|
|
|
* testsuite/gas/mips/pcrel-reloc-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-06-21 21:03:08 +08:00
|
|
|
|
2016-06-21 Graham Markall <graham.markall@embecosm.com>
|
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|
|
|
|
|
|
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|
* config/tc-arc.c (check_cpu_feature, md_parse_option):
|
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|
|
Add nps400 option and feature. Add check for nps400
|
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|
|
|
feature. Refactor existing checks to check subclass before
|
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|
|
|
|
feature enablement.
|
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|
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|
|
(md_show_usage): Document flags for NPS-400 and add some other
|
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|
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|
|
undocumented flags.
|
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|
(cpu_type): Remove nps400 CPU type entry
|
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|
(check_zol): Remove bfd_mach_arc_nps400 case.
|
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|
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|
(md_show_usage): Add help on -mcpu=nps400.
|
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|
(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
|
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set.
|
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|
* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
|
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|
-fpuda flags. Document -mcpu=nps400.
|
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|
* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
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|
|
expected flags to match ARC700 instead of NPS400.
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-6.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-7.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
|
|
|
|
|
|
avoid clash with cbba instruction.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn2op01.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn3op.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn3op.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
|
|
|
|
|
|
-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.
|
|
|
|
|
|
|
2016-06-21 06:36:01 +08:00
|
|
|
|
2016-06-20 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/mips/r6-64-n32.d: Change the `name' tag.
|
|
|
|
|
|
* testsuite/gas/mips/r6-64-n64.d: Likewise.
|
|
|
|
|
|
|
2016-06-21 06:39:20 +08:00
|
|
|
|
2016-06-20 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_fix_adjustable): Update comment on jump
|
|
|
|
|
|
reloc conversion.
|
|
|
|
|
|
|
2016-06-20 16:26:43 +08:00
|
|
|
|
2016-06-20 Virendra Pathak <virendra.pathak@broadcom.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_cpus): Update vulcan feature set.
|
|
|
|
|
|
|
opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.
It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.
Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (rdasr): New macro.
(wrasr): Likewise.
(rdpr): Likewise.
(wrpr): Likewise.
(rdhpr): Likewise.
(wrhpr): Likewise.
(sparc_opcodes): Use the macros above to fix and expand the
definition of read/write instructions from/to
asr/privileged/hyperprivileged instructions.
* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
%hva_mask_nz. Prefer softint_set and softint_clear over
set_softint and clear_softint.
(print_insn_sparc): Support %ver in Rd.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
%hmcddfr and %hva_mask_nz.
(sparc_ip): New handling of asr/privileged/hyperprivileged
registers, adapted to the new form of the sparc opcodes table.
* testsuite/gas/sparc/rdasr.s: New file.
* testsuite/gas/sparc/rdasr.d: Likewise.
* testsuite/gas/sparc/wrasr.s: Likewise.
* testsuite/gas/sparc/wrasr.d: Likewise.
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
wrasr tests.
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
registers require it.
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
registers and write instruction modalities.
* testsuite/gas/sparc/wrpr.d: Likewise.
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
registers.
* testsuite/gas/sparc/rdhpr.d: Likewise.
* testsuite/gas/sparc/wrhpr.s: Likewise.
* testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17 17:15:43 +08:00
|
|
|
|
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
|
|
|
|
|
|
%hmcddfr and %hva_mask_nz.
|
|
|
|
|
|
(sparc_ip): New handling of asr/privileged/hyperprivileged
|
|
|
|
|
|
registers, adapted to the new form of the sparc opcodes table.
|
|
|
|
|
|
* testsuite/gas/sparc/rdasr.s: New file.
|
|
|
|
|
|
* testsuite/gas/sparc/rdasr.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/wrasr.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/wrasr.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
|
|
|
|
|
|
wrasr tests.
|
|
|
|
|
|
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
|
|
|
|
|
|
registers require it.
|
|
|
|
|
|
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
|
|
|
|
|
|
registers and write instruction modalities.
|
|
|
|
|
|
* testsuite/gas/sparc/wrpr.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
|
|
|
|
|
|
registers.
|
|
|
|
|
|
* testsuite/gas/sparc/rdhpr.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/wrhpr.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/wrhpr.d: Likewise.
|
|
|
|
|
|
|
opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 17:14:18 +08:00
|
|
|
|
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
|
|
|
|
|
|
architectures to use the right opcode architecture.
|
|
|
|
|
|
(sparc_md_end): Handle v9{c,d,e,v,m}.
|
|
|
|
|
|
(sparc_ip): Fix some comments.
|
|
|
|
|
|
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
|
|
|
|
|
|
instruction, which is v9d.
|
|
|
|
|
|
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
|
|
|
|
|
|
instruction from the test, as %mwait is not readable.
|
|
|
|
|
|
* testsuite/gas/sparc/mwait.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
|
|
|
|
|
|
mismatch architecture errors.
|
|
|
|
|
|
* testsuite/gas/sparc/mism-2.s: New file.
|
|
|
|
|
|
|
2016-06-17 17:13:30 +08:00
|
|
|
|
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (priv_reg_table): Use NULL instead of the
|
|
|
|
|
|
empty string to mark the end of the array.
|
|
|
|
|
|
(hpriv_reg_table): Likewise.
|
|
|
|
|
|
(v9a_asr_table): Likewise.
|
|
|
|
|
|
(cmp_reg_entry): Handle entries with NULL names.
|
|
|
|
|
|
(F_POP_V9): Define.
|
|
|
|
|
|
(F_POP_PCREL): Likewise.
|
|
|
|
|
|
(F_POP_TLS_CALL): Likewise.
|
|
|
|
|
|
(F_POP_POSTFIX): Likewise.
|
|
|
|
|
|
(struct pop_entry): New type.
|
|
|
|
|
|
(pop_table): New variable.
|
|
|
|
|
|
(enum pop_entry_type): New type.
|
|
|
|
|
|
(struct perc_entry): Likewise.
|
|
|
|
|
|
(NUM_PERC_ENTRIES): Define.
|
|
|
|
|
|
(perc_table): New variable.
|
|
|
|
|
|
(cmp_perc_entry): New function.
|
|
|
|
|
|
(md_begin): Sort hpriv_reg_table and v9a_asr_table, and initialize
|
|
|
|
|
|
perc_table.
|
|
|
|
|
|
(sparc_ip): Handle entries with NULL names in priv_reg_table,
|
|
|
|
|
|
hpriv_reg_table and v9a_asr_table. Use perc_table to handle
|
|
|
|
|
|
%-pseudo-ops.
|
|
|
|
|
|
|
2016-06-15 23:25:34 +08:00
|
|
|
|
2016-06-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the
|
|
|
|
|
|
instruction size.
|
|
|
|
|
|
* config/tc-mcore.c (md_assemble): Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c (md_assemble): Likewise.
|
|
|
|
|
|
* config/tc-moxie.c (md_assemble): Likewise.
|
|
|
|
|
|
* config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32.
|
|
|
|
|
|
* testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of
|
|
|
|
|
|
exception targets. Add alpha, hppa, microblaze and rl78 to list
|
|
|
|
|
|
of exceptions.
|
|
|
|
|
|
(forward): Add microblaze to list of exceptions.
|
|
|
|
|
|
(fwdexp): Add alpha to list of exceptions.
|
|
|
|
|
|
(redef2): Add arm-epoc-pe and rl78 to list of exceptions.
|
|
|
|
|
|
(redef3): Add rl78 and x86_64 cygwin to list of exceptions.
|
|
|
|
|
|
(do_930509a): Alpha sort list of exception targets. Add h8300 and
|
|
|
|
|
|
mn10200 to list of exceptions.
|
|
|
|
|
|
(align2): Expect to fail for nds32.
|
|
|
|
|
|
(cond): Add alpha and rl78 to list of exceptions.
|
|
|
|
|
|
* testsuite/gas/all/none.d: Skip for ft32 and hppa.
|
|
|
|
|
|
* testsuite/gas/all/string.d: Skip for tic4x.
|
|
|
|
|
|
* testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff
|
|
|
|
|
|
target does not support ELF.
|
|
|
|
|
|
* testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target.
|
|
|
|
|
|
* testsuite/gas/cfi/cfi-alpha-2.d: All extended format names.
|
|
|
|
|
|
* testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH
|
|
|
|
|
|
tests for sh-pe and sh-rtemscoff targets.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to
|
|
|
|
|
|
list of exceptions.
|
|
|
|
|
|
(type): Run the noifunc version for alpha-freebsd and visium.
|
|
|
|
|
|
* testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore,
|
|
|
|
|
|
mn10200 or moxie targets.
|
|
|
|
|
|
* testsuite/gas/ft32/insn.d: Update expected disassembly.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin
|
|
|
|
|
|
targets.
|
|
|
|
|
|
* testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for
|
|
|
|
|
|
mcore and rx targets.
|
|
|
|
|
|
* testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k,
|
|
|
|
|
|
rl78 and vax.
|
|
|
|
|
|
(purge): Expect to fail on the ns32k and vax.
|
|
|
|
|
|
* testsuite/gas/nds32/alu-2.d: Update expected disassembly.
|
|
|
|
|
|
* testsuite/gas/nds32/ls.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/nds32/sys-reg.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/nds32/usr-spe-reg.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/pe/aligncomm-d.d: Skip for the sh.
|
|
|
|
|
|
* testsuite/gas/pe/section-align-3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/pe/section-exclude.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ppc/test2xcoff32.d: Pass once all the required
|
|
|
|
|
|
data has been seen.
|
|
|
|
|
|
* testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow
|
|
|
|
|
|
for variations in whitespace.
|
|
|
|
|
|
* testsuite/gas/tilepro/t_constants.d: Pass once all the required
|
|
|
|
|
|
data has been seen.
|
|
|
|
|
|
* testsuite/gas/tilepro/t_constants.s (.safe_word): New macro.
|
|
|
|
|
|
Installs a 32-bit value without generating warnings on 64-bit
|
|
|
|
|
|
hosts.
|
|
|
|
|
|
Use the new macro to replace the .word directives.
|
|
|
|
|
|
|
2016-06-15 04:48:11 +08:00
|
|
|
|
2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/add_s.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/add_s.s: New file.
|
|
|
|
|
|
|
2016-06-15 04:53:04 +08:00
|
|
|
|
2016-06-14 Graham Markall <graham.markall@embecosm.com>
|
2016-06-13 16:03:05 +08:00
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-6.s: Add tests of ldbit.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-6.d: Likewise.
|
|
|
|
|
|
|
2016-06-15 04:53:04 +08:00
|
|
|
|
2016-06-14 Graham Markall <graham.markall@embecosm.com>
|
2016-06-09 15:38:34 +08:00
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-6.s: Add tests of hash, tr, utf8, e4by, and
|
|
|
|
|
|
addf.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-6.d: Likewise.
|
|
|
|
|
|
|
2016-06-15 04:53:04 +08:00
|
|
|
|
2016-06-14 Graham Markall <graham.markall@embecosm.com>
|
2016-06-03 17:48:49 +08:00
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-6.s: Add tests of calcbsd, calcbxd,
|
|
|
|
|
|
calckey, calcxkey, mxb, imxb, addl, subl, andl, orl, xorl, andab, orab,
|
|
|
|
|
|
lbdsize, bdlen, csms, csma, cbba, zncv, and hofs.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-6.d: Likewise.
|
|
|
|
|
|
|
2016-06-14 20:51:10 +08:00
|
|
|
|
2016-06-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nds32.c (nds32_get_align): Avoid left shifting a
|
|
|
|
|
|
signed constant.
|
|
|
|
|
|
|
2016-06-13 23:52:42 +08:00
|
|
|
|
2016-06-13 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_fix_adjustable): Don't convert RELA
|
|
|
|
|
|
JALR relocations on R6.
|
|
|
|
|
|
* testsuite/gas/mips/jal-svr4pic-local.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips1@jal-svr4pic-local.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/r3000@jal-svr4pic-local.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jal-svr4pic-local-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: New
|
|
|
|
|
|
test.
|
|
|
|
|
|
* testsuite/gas/mips/jal-svr4pic-local-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: New
|
|
|
|
|
|
test.
|
|
|
|
|
|
* testsuite/gas/mips/jal-svr4pic-local.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/jal-svr4pic-local-newabi.s: New test
|
|
|
|
|
|
source.
|
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|
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|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
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|
2016-06-13 21:17:31 +08:00
|
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|
2016-06-13 Virendra Pathak <virendra.pathak@broadcom.com>
|
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|
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|
|
|
|
* config/tc-aarch64.c (aarch64_cpus): Add Broadcom Vulcan.
|
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|
* doc/c-aarch64.texi: Document that vulcan is a valid processor
|
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|
name.
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|
2016-06-13 17:49:26 +08:00
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|
2016-06-13 Nick Clifton <nickc@redhat.com>
|
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|
* config/tc-arm.c: For non-ELF based targets skip ARM feature sets
|
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|
|
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|
that are not supported.
|
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|
|
* config/tc-arc.c (md_apply_fix): Avoid left shifting a signed
|
|
|
|
|
|
constant.
|
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|
|
|
|
* config/tc-cr16.c (check_range): Likewise.
|
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|
|
|
|
* config/tc-nios2.c (nios2_check_overflow): Likewise.
|
|
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|
2016-06-09 17:08:08 +08:00
|
|
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|
2016-06-08 Renlin Li <renlin.li@arm.com>
|
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|
* config/tc-aarch64.c (print_operands): Substitute size.
|
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|
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|
(output_operand_error_record): Likewise.
|
|
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|
|
PowerPC VLE
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE. For
example
{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe. Also, we don't check
user assembly against the processor type as well as we could.
Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31. Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.
This patch fixes those problems in the opcode table, and removes
PPCNONE. I find a plain 0 distracts less from other values.
In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects. It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.
include/
* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
PPC_APUINFO_VLE: Define.
opcodes/
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
cpu for "vle" to e500.
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
(PPCNONE): Delete, substitute throughout.
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
except for major opcode 4 and 31.
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
to match other 32-bit archs.
* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
(ppc_elf_object_p): Call it.
(ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
overlong line.
(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
_bfd_elf_ppc_at_tprel_transform): Move to..
* elf-bfd.h: ..here.
(_bfd_elf_ppc_set_arch): Declare.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
* testsuite/ld-powerpc/apuinfo-vle2.s: New.
* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-07 20:34:38 +08:00
|
|
|
|
2016-06-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
|
|
|
|
|
|
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
|
|
|
|
|
|
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
|
|
|
|
|
|
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
|
|
|
|
|
|
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
|
|
|
|
|
|
add vle_opcodes twice.
|
|
|
|
|
|
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
|
|
|
|
|
|
|
2016-06-07 16:56:42 +08:00
|
|
|
|
2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.
|
|
|
|
|
|
(arm_ext_ras): Renamed from arm_ext_v8_2.
|
|
|
|
|
|
(insns): Update for arm_ext_v8_2 renaming.
|
|
|
|
|
|
(arm_extensions): Add "ras".
|
|
|
|
|
|
* doc/c-arm.texi (ARM Options): Add an entry for "ras".
|
|
|
|
|
|
* testsuite/gas/arm/armv8-a+ras.d: New.
|
|
|
|
|
|
* testsuite/gas/arm/armv8_2-a.d: Add explicit command line
|
|
|
|
|
|
options.
|
|
|
|
|
|
|
2016-05-24 20:59:35 +08:00
|
|
|
|
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* itbl-parse.y (yyerror): Use modern argument declaration style.
|
|
|
|
|
|
|
2016-05-29 10:31:07 +08:00
|
|
|
|
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sh.c (parse_reg): Change type of mode argument to
|
|
|
|
|
|
sh_arg_type.
|
|
|
|
|
|
(get_operand): Adjust.
|
|
|
|
|
|
(insert): Change type of how to bfd_reloc_code_real_type.
|
|
|
|
|
|
(insert4): Likewise.
|
|
|
|
|
|
* config/tc-sh64.c (shmedia_get_operand): Adjust.
|
|
|
|
|
|
(shmedia_parse_reg): Change type of mode to shmedia_arg_type.
|
|
|
|
|
|
|
2016-05-29 05:57:44 +08:00
|
|
|
|
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nds32.c (nds32_parse_option): Make the type of ptr_arg
|
|
|
|
|
|
const char *.
|
|
|
|
|
|
|
Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
opcodes/
PR binutils/20196
* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
opcodes for E6500.
gas/
PR binutils/20196
* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
stbcx., sthcx., stwcx., stdcx.>: Add tests.
* gas/testsuite/gas/ppc/e6500.d: Likewise.
* gas/testsuite/gas/ppc/power8.s: Likewise.
* gas/testsuite/gas/ppc/power8.d: Likewise.
* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
stdcx.>: Add tests.
* gas/testsuite/gas/ppc/power4.d: Likewise.
2016-06-04 07:38:02 +08:00
|
|
|
|
2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/20196
|
|
|
|
|
|
* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
|
|
|
|
|
|
stbcx., sthcx., stwcx., stdcx.>: Add tests.
|
|
|
|
|
|
* gas/testsuite/gas/ppc/e6500.d: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/ppc/power8.s: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/ppc/power8.d: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
|
|
|
|
|
|
stdcx.>: Add tests.
|
|
|
|
|
|
* gas/testsuite/gas/ppc/power4.d: Likewise.
|
|
|
|
|
|
|
2016-06-04 06:55:29 +08:00
|
|
|
|
2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutis/18386
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch.d: Updated.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-4.l: New file.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-branch-4.s: Likewise.
|
|
|
|
|
|
|
2016-06-03 23:59:24 +08:00
|
|
|
|
2016-06-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a73 entry.
|
|
|
|
|
|
* doc/c-aarch64.texi (-mcpu): Document cortex-a73 value.
|
|
|
|
|
|
|
2016-06-03 23:58:21 +08:00
|
|
|
|
2016-06-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_cpus): Add cortex-a73 entry.
|
|
|
|
|
|
* doc/c-arm.texi (-mcpu=): Document cortex-a73 value.
|
|
|
|
|
|
|
2016-06-02 22:03:47 +08:00
|
|
|
|
2016-06-02 Vineet Gupta <Vineet.Gupta1@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt: Replace -uclibc with *.
|
|
|
|
|
|
|
2016-06-02 21:03:23 +08:00
|
|
|
|
2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (parse_opcode_flags): New function.
|
|
|
|
|
|
(find_opcode_match): Move flag parsing code out to new function.
|
|
|
|
|
|
Ignore operands marked IGNORE.
|
|
|
|
|
|
(build_fake_opcode_hash_entry): New function.
|
|
|
|
|
|
(find_special_case_long_opcode): New function.
|
|
|
|
|
|
(find_special_case): Lookup long opcodes.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-7.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-7.s: New file.
|
|
|
|
|
|
|
2016-05-29 13:04:01 +08:00
|
|
|
|
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ns32k.c: Remove definition of input_line_pointer.
|
|
|
|
|
|
|
2016-05-13 14:51:41 +08:00
|
|
|
|
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-avr.c (avr_parse_cons_expression): Replace iteration to
|
|
|
|
|
|
sentinal with iteration to array size.
|
|
|
|
|
|
|
2016-03-28 17:42:02 +08:00
|
|
|
|
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/xtensa-relax.h: Move typedefs of enums to the enums
|
|
|
|
|
|
definition.
|
|
|
|
|
|
|
2016-05-29 13:04:15 +08:00
|
|
|
|
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ns32k.c (bit_fix_new): Replace obstack-alloc with XOBNEW
|
|
|
|
|
|
macro.
|
|
|
|
|
|
|
Add support for some variants of the ARC nps400 rflt instruction.
gas * testsuite/gas/arc/nps-400-1.s: Add rflt variants with
operands of types a,b,u6, 0,b,u6, and 0,b,limm.
* testsuite/gas/arc/nps-400-1.d: Likewise.
opcodes * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
0,b,limm to the rflt instruction.
2016-06-01 23:29:27 +08:00
|
|
|
|
2016-06-01 Graham Markall <graham.markall@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-1.s: Add rflt variants with
|
|
|
|
|
|
operands of types a,b,u6, 0,b,u6, and 0,b,limm.
|
|
|
|
|
|
* testsuite/gas/arc/nps-400-1.d: Likewise.
|
|
|
|
|
|
|
2016-05-29 23:26:43 +08:00
|
|
|
|
2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20145
|
|
|
|
|
|
* config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd,
|
|
|
|
|
|
noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl,
|
|
|
|
|
|
noavx512ifma and noavx512vbmi.
|
|
|
|
|
|
* doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er,
|
|
|
|
|
|
noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma
|
|
|
|
|
|
and noavx512vbmi.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2.
|
|
|
|
|
|
* testsuite/gas/i386/noavx512-1.l: New file.
|
|
|
|
|
|
* testsuite/gas/i386/noavx512-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/noavx512-2.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/noavx512-2.s: Likewise.
|
|
|
|
|
|
|
Update x86 CPU_XXX_FLAGS handling
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update
CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable
MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when
disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C,
FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687,
nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives
to x86 assembler.
TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler.
gas/
PR gas/20145
* config/tc-i386.c (cpu_arch): Add 687.
(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
nosse4.1, nosse4.2, nosse4 and noavx2.
(parse_real_register): Check cpuregmmx instead of cpummx for MMX
register. Check cpuregxmm instead of cpusse for XMM register.
Check cpuregymm instead of cpuavx for YMM register. Check
cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
* testsuite/gas/i386/arch-10.d (as): Likewise.
* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3
and noavx-4.
* testsuite/gas/i386/no87-3.l: New file.
* testsuite/gas/i386/no87-3.s: Likewise.
* testsuite/gas/i386/noavx-3.l: Likewise.
* testsuite/gas/i386/noavx-3.s: Likewise.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-4.s: Likewise.
* testsuite/gas/i386/nosse-4.l: Likewise.
* testsuite/gas/i386/nosse-4.s: Likewise.
* testsuite/gas/i386/nosse-5.d: Likewise.
* testsuite/gas/i386/nosse-5.s: Likewise.
opcodes/
PR gas/20145
* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
CpuRegMask for AVX512.
(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
and CpuRegMask.
(set_bitfield_from_cpu_flag_init): New function.
(set_bitfield): Remove const on f. Call
set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
* i386-opc.h (CpuRegMMX): New.
(CpuRegXMM): Likewise.
(CpuRegYMM): Likewise.
(CpuRegZMM): Likewise.
(CpuRegMask): Likewise.
(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
and cpuregmask.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-05-28 01:05:39 +08:00
|
|
|
|
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20145
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add 687.
|
|
|
|
|
|
(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
|
|
|
|
|
|
nosse4.1, nosse4.2, nosse4 and noavx2.
|
|
|
|
|
|
(parse_real_register): Check cpuregmmx instead of cpummx for MMX
|
|
|
|
|
|
register. Check cpuregxmm instead of cpusse for XMM register.
|
|
|
|
|
|
Check cpuregymm instead of cpuavx for YMM register. Check
|
|
|
|
|
|
cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
|
|
|
|
|
|
* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
|
|
|
|
|
|
nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
|
|
|
|
|
|
* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
|
|
|
|
|
|
* testsuite/gas/i386/arch-10.d (as): Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
|
|
|
|
|
|
arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3
|
|
|
|
|
|
and noavx-4.
|
|
|
|
|
|
* testsuite/gas/i386/no87-3.l: New file.
|
|
|
|
|
|
* testsuite/gas/i386/no87-3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/noavx-3.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/noavx-3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/noavx-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/noavx-4.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-4.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-4.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-5.s: Likewise.
|
|
|
|
|
|
|
2016-05-27 23:02:56 +08:00
|
|
|
|
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20154
|
|
|
|
|
|
* config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor
|
|
|
|
|
|
cpuintel64.
|
|
|
|
|
|
(match_template): Check Intel64/AMD64 ISA.
|
|
|
|
|
|
|
2016-05-27 21:55:42 +08:00
|
|
|
|
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20154
|
|
|
|
|
|
* config/tc-i386.c (intel64): New.
|
|
|
|
|
|
(cpu_flags_match): Set cpuamd64 and cpuintel64.
|
|
|
|
|
|
(md_parse_option): Set intel64 instead of cpuamd64 and
|
|
|
|
|
|
cpuintel64.
|
|
|
|
|
|
|
2016-05-27 19:56:05 +08:00
|
|
|
|
2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_flags_match): Don't clear cpu64 nor
|
|
|
|
|
|
cpuno64.
|
|
|
|
|
|
|
2016-05-27 08:06:51 +08:00
|
|
|
|
2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/altivec3.d <vmsumudm>: Add test.
|
|
|
|
|
|
* testsuite/gas/ppc/altivec3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.d <addex[.], lwzmx, vmsumudm>: Add tests.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.s: Likewise.
|
|
|
|
|
|
|
2016-05-26 22:55:38 +08:00
|
|
|
|
2016-05-26 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/avx512vl-2.l: Append "#pass".
|
|
|
|
|
|
* testsuite/gas/i386/noavx-1.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nommx-1.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-1.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/avx512vl-2.s: Append ".p2align 4".
|
|
|
|
|
|
* testsuite/gas/i386/noavx-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nommx-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
|
|
|
|
|
|
|
2016-05-23 19:42:14 +08:00
|
|
|
|
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-metag.c (metag_handle_align): Make the type of noop
|
|
|
|
|
|
unsigned char.
|
|
|
|
|
|
|
2016-05-22 10:24:24 +08:00
|
|
|
|
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-rx.c (md_convert_frag): Make the type of reloc_type
|
|
|
|
|
|
bfd_reloc_code_real_type.
|
|
|
|
|
|
|
2016-05-26 05:59:05 +08:00
|
|
|
|
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20140
|
|
|
|
|
|
* config/tc-i386.c (cpu_flags_match): Require another match
|
|
|
|
|
|
for AVX512VL.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2,
|
|
|
|
|
|
x86-64-avx512vl-1 and x86-64-avx512vl-2.
|
|
|
|
|
|
* testsuite/gas/i386/avx512vl-1.l: New file.
|
|
|
|
|
|
* testsuite/gas/i386/avx512vl-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/avx512vl-2.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/avx512vl-2.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
|
|
|
|
|
|
|
2016-05-26 01:49:25 +08:00
|
|
|
|
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/20141
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run x86-64-pr20141.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-pr20141.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-pr20141.s: Likewise.
|
|
|
|
|
|
|
2016-05-26 01:25:50 +08:00
|
|
|
|
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (arch_entry): Remove negated.
|
|
|
|
|
|
(noarch_entry): New struct.
|
|
|
|
|
|
(cpu_arch): Updated. Remove .no87, .nommx, .nosse and .noavx.
|
|
|
|
|
|
(cpu_noarch): New.
|
|
|
|
|
|
(set_cpu_arch): Check cpu_noarch after cpu_arch.
|
|
|
|
|
|
(md_parse_option): Allow -march=+nosse. Check cpu_noarch after
|
|
|
|
|
|
cpu_arch.
|
|
|
|
|
|
(output_message): New function.
|
|
|
|
|
|
(show_arch): Use it. Handle cpu_noarch.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3,
|
|
|
|
|
|
nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2.
|
|
|
|
|
|
* testsuite/gas/i386/noavx-1.l: New file.
|
|
|
|
|
|
* testsuite/gas/i386/noavx-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/noavx-2.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/noavx-2.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nommx-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nommx-1.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nommx-2.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nommx-2.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nommx-3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nommx-3.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-1.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-2.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-2.l: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/nosse-3.l: Likewise.
|
|
|
|
|
|
|
2016-05-25 20:09:51 +08:00
|
|
|
|
2016-05-25 Chua Zheng Leong <chuazl@comp.nus.edu.sg>
|
|
|
|
|
|
|
2016-05-25 20:12:14 +08:00
|
|
|
|
PR target/20067
|
2016-05-25 20:09:51 +08:00
|
|
|
|
* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
|
|
|
|
|
|
instruction if supported by the currently selected fpu variant.
|
|
|
|
|
|
* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
|
|
|
|
|
|
* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
|
|
|
|
|
|
|
2016-05-24 20:54:31 +08:00
|
|
|
|
2016-05-24 Maciej W. Rozycki <macro@imgtec.com>
|
2016-05-25 20:09:51 +08:00
|
|
|
|
|
2016-05-24 20:54:31 +08:00
|
|
|
|
* config/tc-mips.c (mips_fix_adjustable): Also return 0 for
|
|
|
|
|
|
jump relocations against MIPS16 or microMIPS symbols on RELA
|
|
|
|
|
|
targets.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-local.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-local-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-local-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-local.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-05-24 21:05:19 +08:00
|
|
|
|
2016-05-24 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_apply_fix)
|
|
|
|
|
|
<BFD_RELOC_MIPS16_TLS_TPREL_LO16>: Remove fall-through, adjust
|
|
|
|
|
|
code accordingly.
|
|
|
|
|
|
|
2016-05-23 12:39:47 +08:00
|
|
|
|
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (struct suffix_reloc_map): Change type of field
|
|
|
|
|
|
operator to operatorT.
|
|
|
|
|
|
(map_suffix_reloc_to_operator): Change return type to operatorT.
|
|
|
|
|
|
|
2016-05-22 15:39:00 +08:00
|
|
|
|
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-d30v.c (find_format): Change type of X_op to operatorT.
|
|
|
|
|
|
|
2016-05-22 12:32:22 +08:00
|
|
|
|
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mmix.c (mmix_parse_predefined_name): Change type of
|
|
|
|
|
|
handler_charp to const char *.
|
|
|
|
|
|
|
2016-05-21 16:21:32 +08:00
|
|
|
|
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ft32.h (DEFAULT_TARGET_FORMAT): Remove.
|
|
|
|
|
|
(ft32_target_format): Likewise.
|
|
|
|
|
|
(TARGET_FORMAT): Adjust.
|
|
|
|
|
|
|
2016-05-20 18:33:35 +08:00
|
|
|
|
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ia64.c (dot_rot): simplify allocations from obstacks.
|
|
|
|
|
|
(ia64_frob_label): Likewise.
|
|
|
|
|
|
|
2016-05-13 16:05:59 +08:00
|
|
|
|
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-cr16.c (check_range): Make type of retval op_err.
|
|
|
|
|
|
* config/tc-crx.c: Likewise.
|
|
|
|
|
|
|
2016-05-19 18:33:17 +08:00
|
|
|
|
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (md_begin): Add XY registers.
|
|
|
|
|
|
(cpu_types): Code density is default off for ARC EM.
|
|
|
|
|
|
|
2016-05-23 23:25:46 +08:00
|
|
|
|
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (attributes_t): Renamed attribute class to
|
|
|
|
|
|
attr_class.
|
|
|
|
|
|
(find_opcode_match, assemble_insn, tokenize_extinsn): Changed.
|
|
|
|
|
|
|
2016-05-23 20:56:46 +08:00
|
|
|
|
2016-05-23 Kuba Sejdak <jakub.sejdak@phoesys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configuse.tgt: Add entry for arm-phoenix.
|
|
|
|
|
|
|
2016-05-19 10:48:34 +08:00
|
|
|
|
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-tic54x.c (tic54x_sect): simplify string creation.
|
|
|
|
|
|
|
2016-05-19 10:39:18 +08:00
|
|
|
|
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-spu.c (APUOP): Use OPCODE as an unsigned constant.
|
|
|
|
|
|
|
2016-05-19 11:48:48 +08:00
|
|
|
|
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-tic54x.c (tic54x_mmregs): Adjust.
|
|
|
|
|
|
(md_begin): Likewise.
|
|
|
|
|
|
(encode_condition): Likewise.
|
|
|
|
|
|
(encode_cc3): Likewise.
|
|
|
|
|
|
(encode_cc2): Likewise.
|
|
|
|
|
|
(encode_operand): Likewise.
|
|
|
|
|
|
(tic54x_undefined_symbol): Likewise.
|
|
|
|
|
|
|
2016-05-20 22:20:42 +08:00
|
|
|
|
2016-05-20 Matthew Fortune <matthew.fortune@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_cpu_info_table): Update comment. Add
|
|
|
|
|
|
p6600 entry.
|
|
|
|
|
|
* doc/c-mips.texi: Document p6600 -march option.
|
|
|
|
|
|
|
2016-05-20 21:01:28 +08:00
|
|
|
|
2016-05-20 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19600
|
|
|
|
|
|
* config/tc-i386.c (md_apply_fix): Preserve addend for
|
|
|
|
|
|
BFD_RELOC_386_GOT32 and BFD_RELOC_X86_64_GOT32.
|
|
|
|
|
|
* testsuite/gas/i386/addend.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/addend.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-addend.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-addend.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run addend and x86-64-addend.
|
|
|
|
|
|
* testsuite/gas/i386/reloc32.d: Updated.
|
|
|
|
|
|
|
2016-05-20 20:32:19 +08:00
|
|
|
|
2016-05-20 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (append_insn): Correct the encoding of a
|
|
|
|
|
|
constant argument for microMIPS JALX.
|
|
|
|
|
|
(tc_gen_reloc): Correct the encoding of an in-place addend for
|
|
|
|
|
|
microMIPS JALX.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-addend.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-addend-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-addend-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-imm.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-imm-n32.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-imm-n64.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-addend.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/jalx-imm.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-05-20 19:41:50 +08:00
|
|
|
|
2016-05-20 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c: Correct tab-after-space formatting mistakes
|
|
|
|
|
|
throughout.
|
|
|
|
|
|
|
2016-05-06 20:59:03 +08:00
|
|
|
|
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (find_opcode_match): Remove casting away of
|
|
|
|
|
|
const.
|
|
|
|
|
|
* config/tc-arc.h (struct arc_flags): Make flgp field const.
|
|
|
|
|
|
|
2016-05-04 21:11:11 +08:00
|
|
|
|
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (md_pcrel_from_section): Use BFD_VMA_FMT where
|
|
|
|
|
|
appropriate.
|
|
|
|
|
|
(md_convert_frag): Likewise.
|
|
|
|
|
|
|
2016-05-04 20:57:10 +08:00
|
|
|
|
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (arc_opcode_hash_entry_iterator_next): Set
|
|
|
|
|
|
cached opcode to NULL when we reach a non-matching opcode.
|
|
|
|
|
|
* testsuite/gas/arc/asm-errors-2.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/asm-errors-2.err: New file.
|
|
|
|
|
|
* testsuite/gas/arc/asm-errors-2.s: New file.
|
|
|
|
|
|
|
2016-05-03 20:43:44 +08:00
|
|
|
|
2016-05-18 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (tokenize_arguments): Add checks for array
|
|
|
|
|
|
overflow.
|
|
|
|
|
|
* testsuite/gas/arc/asm-errors.s: Addition test line added.
|
|
|
|
|
|
* testsuite/gas/arc/asm-errors.err: Update expected results.
|
|
|
|
|
|
|
2016-05-14 16:33:53 +08:00
|
|
|
|
2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-rx.c (struct cpu_type): Change the type of a field from
|
|
|
|
|
|
int to enum rx_cpu_types.
|
|
|
|
|
|
|
2016-05-14 14:34:23 +08:00
|
|
|
|
2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-dlx.c (struct machine_it): change the type of a field from
|
|
|
|
|
|
int to bfd_reloc_code_real_type.
|
|
|
|
|
|
* config/tc-tic4x.c: Likewise.
|
|
|
|
|
|
|
2016-05-18 18:17:33 +08:00
|
|
|
|
2016-05-18 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-v850.c (v850_target_arch): change type to enum
|
|
|
|
|
|
bfd_architecture.
|
|
|
|
|
|
* config/tc-v850.h (v850_target_arch): Likewise.
|
|
|
|
|
|
|
2016-05-18 09:57:56 +08:00
|
|
|
|
2016-05-18 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (ppc_insert_operand): Trim PPC_OPERAND_SIGNOPT
|
|
|
|
|
|
allowed negative range.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.s: Test xxspltib of -128, not -256.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.d: Update.
|
|
|
|
|
|
|
2016-05-17 23:35:12 +08:00
|
|
|
|
2016-05-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Force Thumb when
|
|
|
|
|
|
disassembling and stop skipping targets.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-base.d: Also allow nops after the last
|
|
|
|
|
|
instruction for targets that have stronger alignment requirement.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m.s: Add label.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-main.s: Likewise.
|
|
|
|
|
|
|
2016-05-15 04:31:45 +08:00
|
|
|
|
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m32r.c (mach_table): Make static and const.
|
|
|
|
|
|
|
2016-05-14 14:34:02 +08:00
|
|
|
|
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-vax.c (flonum_gen2vax): Adjust prototype to match
|
|
|
|
|
|
definition.
|
|
|
|
|
|
|
2016-05-14 12:34:05 +08:00
|
|
|
|
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mn10300.c (md_begin): set linkrelax here instead of
|
|
|
|
|
|
defining it.
|
|
|
|
|
|
* config/tc-msp430.c (md_begin): Likewise.
|
|
|
|
|
|
|
2016-05-15 03:27:26 +08:00
|
|
|
|
2016-05-16 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m68hc11.c (fixup8): Change variables type from int to
|
|
|
|
|
|
bfd_reloc_code_real_type where appropriate.
|
|
|
|
|
|
(fixup16): Likewise.
|
|
|
|
|
|
(fixup8_xg): Likewise.
|
|
|
|
|
|
|
2016-05-16 06:14:52 +08:00
|
|
|
|
2016-05-15 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sh64.c (shmedia_check_limits): Constify `msg'.
|
|
|
|
|
|
|
2016-05-14 04:15:00 +08:00
|
|
|
|
2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/power9.d <xxspltib>: Add additional operand tests.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.s: Likewise.
|
|
|
|
|
|
|
2016-05-13 14:27:10 +08:00
|
|
|
|
2016-05-13 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-coff.c (weak_uniquify): Delete unused var.
|
|
|
|
|
|
|
2016-04-07 04:26:46 +08:00
|
|
|
|
2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* app.c (app_push): Use XNEW and related macros.
|
|
|
|
|
|
* as.c (parse_args): Likewise.
|
|
|
|
|
|
* cgen.c (make_right_shifted_expr): Likewise.
|
|
|
|
|
|
(gas_cgen_tc_gen_reloc): Likewise.
|
|
|
|
|
|
* config/bfin-defs.h: Likewise.
|
|
|
|
|
|
* config/bfin-parse.y: Likewise.
|
|
|
|
|
|
* config/obj-coff.c (stack_init): Likewise.
|
|
|
|
|
|
(stack_push): Likewise.
|
|
|
|
|
|
(coff_obj_symbol_new_hook): Likewise.
|
|
|
|
|
|
(coff_obj_symbol_clone_hook): Likewise.
|
|
|
|
|
|
(add_lineno): Likewise.
|
|
|
|
|
|
(coff_frob_symbol): Likewise.
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_section_name): Likewise.
|
|
|
|
|
|
(build_group_lists): Likewise.
|
|
|
|
|
|
* config/obj-evax.c (evax_symbol_new_hook): Likewise.
|
|
|
|
|
|
* config/obj-macho.c (obj_mach_o_indirect_symbol): Likewise.
|
|
|
|
|
|
* config/tc-aarch64.c (insert_reg_alias): Likewise.
|
|
|
|
|
|
(find_or_make_literal_pool): Likewise.
|
|
|
|
|
|
(add_to_lit_pool): Likewise.
|
|
|
|
|
|
(fill_instruction_hash_table): Likewise.
|
|
|
|
|
|
* config/tc-alpha.c (load_expression): Likewise.
|
|
|
|
|
|
(emit_jsrjmp): Likewise.
|
|
|
|
|
|
(s_alpha_ent): Likewise.
|
|
|
|
|
|
(s_alpha_end): Likewise.
|
|
|
|
|
|
(s_alpha_linkage): Likewise.
|
|
|
|
|
|
(md_begin): Likewise.
|
|
|
|
|
|
(tc_gen_reloc): Likewise.
|
|
|
|
|
|
* config/tc-arc.c (arc_insert_opcode): Likewise.
|
|
|
|
|
|
(arc_extcorereg): Likewise.
|
|
|
|
|
|
* config/tc-bfin.c: Likewise.
|
|
|
|
|
|
* config/tc-cr16.c: Likewise.
|
|
|
|
|
|
* config/tc-cris.c: Likewise.
|
|
|
|
|
|
* config/tc-crx.c (preprocess_reglist): Likewise.
|
|
|
|
|
|
* config/tc-d10v.c: Likewise.
|
|
|
|
|
|
* config/tc-frv.c (frv_insert_vliw_insn): Likewise.
|
|
|
|
|
|
(frv_tomcat_shuffle): Likewise.
|
|
|
|
|
|
* config/tc-h8300.c: Likewise.
|
|
|
|
|
|
* config/tc-i370.c (i370_macro): Likewise.
|
|
|
|
|
|
* config/tc-i386.c (lex_got): Likewise.
|
|
|
|
|
|
(md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-ia64.c (alloc_record): Likewise.
|
|
|
|
|
|
(set_imask): Likewise.
|
|
|
|
|
|
(save_prologue_count): Likewise.
|
|
|
|
|
|
(dot_proc): Likewise.
|
|
|
|
|
|
(dot_endp): Likewise.
|
|
|
|
|
|
(ia64_frob_label): Likewise.
|
|
|
|
|
|
(add_qp_imply): Likewise.
|
|
|
|
|
|
(add_qp_mutex): Likewise.
|
|
|
|
|
|
(mark_resource): Likewise.
|
|
|
|
|
|
(dot_alias): Likewise.
|
|
|
|
|
|
* config/tc-m68hc11.c: Likewise.
|
|
|
|
|
|
* config/tc-m68k.c (m68k_frob_label): Likewise.
|
|
|
|
|
|
(s_save): Likewise.
|
|
|
|
|
|
(mri_control_label): Likewise.
|
|
|
|
|
|
(push_mri_control): Likewise.
|
|
|
|
|
|
(build_mri_control_operand): Likewise.
|
|
|
|
|
|
(s_mri_else): Likewise.
|
|
|
|
|
|
(s_mri_break): Likewise.
|
|
|
|
|
|
(s_mri_next): Likewise.
|
|
|
|
|
|
(s_mri_for): Likewise.
|
|
|
|
|
|
(s_mri_endw): Likewise.
|
|
|
|
|
|
* config/tc-metag.c (create_mnemonic_htab): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.c: Likewise.
|
|
|
|
|
|
* config/tc-mmix.c (s_loc): Likewise.
|
|
|
|
|
|
* config/tc-nds32.c (nds32_relax_hint): Likewise.
|
|
|
|
|
|
* config/tc-nios2.c (nios2_insn_reloc_new): Likewise.
|
|
|
|
|
|
* config/tc-rl78.c: Likewise.
|
|
|
|
|
|
* config/tc-rx.c (rx_include): Likewise.
|
|
|
|
|
|
* config/tc-sh.c: Likewise.
|
|
|
|
|
|
* config/tc-sh64.c (shmedia_frob_section_type): Likewise.
|
|
|
|
|
|
* config/tc-sparc.c: Likewise.
|
|
|
|
|
|
* config/tc-spu.c: Likewise.
|
|
|
|
|
|
* config/tc-tic6x.c (static tic6x_unwind_info *tic6x_get_unwind): Likewise.
|
|
|
|
|
|
(tic6x_start_unwind_section): Likewise.
|
|
|
|
|
|
* config/tc-tilegx.c: Likewise.
|
|
|
|
|
|
* config/tc-tilepro.c: Likewise.
|
|
|
|
|
|
* config/tc-v850.c: Likewise.
|
|
|
|
|
|
* config/tc-visium.c: Likewise.
|
|
|
|
|
|
* config/tc-xgate.c: Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_translate_old_userreg_ops): Likewise.
|
|
|
|
|
|
(new_resource_table): Likewise.
|
|
|
|
|
|
(resize_resource_table): Likewise.
|
|
|
|
|
|
(xtensa_create_trampoline_frag): Likewise.
|
|
|
|
|
|
(xtensa_maybe_create_literal_pool_frag): Likewise.
|
|
|
|
|
|
(cache_literal_section): Likewise.
|
|
|
|
|
|
* config/xtensa-relax.c (append_transition): Likewise.
|
|
|
|
|
|
(append_condition): Likewise.
|
|
|
|
|
|
(append_value_condition): Likewise.
|
|
|
|
|
|
(append_constant_value_condition): Likewise.
|
|
|
|
|
|
(append_literal_op): Likewise.
|
|
|
|
|
|
(append_label_op): Likewise.
|
|
|
|
|
|
(append_constant_op): Likewise.
|
|
|
|
|
|
(append_field_op): Likewise.
|
|
|
|
|
|
(append_user_fn_field_op): Likewise.
|
|
|
|
|
|
(enter_opname_n): Likewise.
|
|
|
|
|
|
(enter_opname): Likewise.
|
|
|
|
|
|
(split_string): Likewise.
|
|
|
|
|
|
(parse_insn_templ): Likewise.
|
|
|
|
|
|
(clone_req_or_option_list): Likewise.
|
|
|
|
|
|
(clone_req_option_list): Likewise.
|
|
|
|
|
|
(parse_option_cond): Likewise.
|
|
|
|
|
|
(parse_insn_pattern): Likewise.
|
|
|
|
|
|
(parse_insn_repl): Likewise.
|
|
|
|
|
|
(build_transition): Likewise.
|
|
|
|
|
|
(build_transition_table): Likewise.
|
|
|
|
|
|
* dw2gencfi.c (alloc_fde_entry): Likewise.
|
|
|
|
|
|
(alloc_cfi_insn_data): Likewise.
|
|
|
|
|
|
(cfi_add_CFA_remember_state): Likewise.
|
|
|
|
|
|
(dot_cfi_escape): Likewise.
|
|
|
|
|
|
(dot_cfi_fde_data): Likewise.
|
|
|
|
|
|
(select_cie_for_fde): Likewise.
|
|
|
|
|
|
* dwarf2dbg.c (dwarf2_directive_loc): Likewise.
|
|
|
|
|
|
* ecoff.c (ecoff_add_bytes): Likewise.
|
|
|
|
|
|
(ecoff_build_debug): Likewise.
|
|
|
|
|
|
* input-scrub.c (input_scrub_push): Likewise.
|
|
|
|
|
|
(input_scrub_begin): Likewise.
|
|
|
|
|
|
(input_scrub_next_buffer): Likewise.
|
|
|
|
|
|
* itbl-ops.c (append_insns_as_macros): Likewise.
|
|
|
|
|
|
(alloc_entry): Likewise.
|
|
|
|
|
|
(alloc_field): Likewise.
|
|
|
|
|
|
* listing.c (listing_newline): Likewise.
|
|
|
|
|
|
(listing_listing): Likewise.
|
|
|
|
|
|
* macro.c (get_any_string): Likewise.
|
|
|
|
|
|
(delete_macro): Likewise.
|
|
|
|
|
|
* stabs.c (generate_asm_file): Likewise.
|
|
|
|
|
|
(stabs_generate_asm_lineno): Likewise.
|
|
|
|
|
|
* subsegs.c (subseg_change): Likewise.
|
|
|
|
|
|
(subseg_get): Likewise.
|
|
|
|
|
|
* symbols.c (define_dollar_label): Likewise.
|
|
|
|
|
|
(symbol_relc_make_sym): Likewise.
|
|
|
|
|
|
* write.c (write_relocs): Likewise.
|
|
|
|
|
|
|
2016-03-28 17:49:15 +08:00
|
|
|
|
2016-05-13 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-coff.c (obj_coff_def): Simplify string copying.
|
|
|
|
|
|
(weak_name2altname): Likewise.
|
|
|
|
|
|
(weak_uniquify): Likewise.
|
|
|
|
|
|
(obj_coff_section): Likewise.
|
|
|
|
|
|
(obj_coff_init_stab_section): Likewise.
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_section_name): Likewise.
|
|
|
|
|
|
(obj_elf_init_stab_section): Likewise.
|
|
|
|
|
|
* config/obj-evax.c (evax_shorten_name): Likewise.
|
|
|
|
|
|
* config/obj-macho.c (obj_mach_o_make_or_get_sect): Likewise.
|
|
|
|
|
|
* config/tc-aarch64.c (create_register_alias): Likewise.
|
|
|
|
|
|
* config/tc-alpha.c (load_expression): Likewise.
|
|
|
|
|
|
(s_alpha_file): Likewise.
|
|
|
|
|
|
(s_alpha_section_name): Likewise.
|
|
|
|
|
|
(tc_gen_reloc): Likewise.
|
|
|
|
|
|
* config/tc-arc.c (md_assemble): Likewise.
|
|
|
|
|
|
* config/tc-arm.c (create_neon_reg_alias): Likewise.
|
|
|
|
|
|
(start_unwind_section): Likewise.
|
|
|
|
|
|
* config/tc-hppa.c (pa_build_unwind_subspace): Likewise.
|
|
|
|
|
|
(hppa_elf_mark_end_of_function): Likewise.
|
|
|
|
|
|
* config/tc-nios2.c (nios2_modify_arg): Likewise.
|
|
|
|
|
|
(nios2_negate_arg): Likewise.
|
|
|
|
|
|
* config/tc-rx.c (rx_section): Likewise.
|
|
|
|
|
|
* config/tc-sh64.c (sh64_consume_datalabel): Likewise.
|
|
|
|
|
|
* config/tc-tic30.c (tic30_find_parallel_insn): Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c (tic54x_include): Likewise.
|
|
|
|
|
|
(tic54x_macro_info): Likewise.
|
|
|
|
|
|
(subsym_get_arg): Likewise.
|
|
|
|
|
|
(subsym_substitute): Likewise.
|
|
|
|
|
|
(tic54x_start_line_hook): Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_literal_prefix): Likewise.
|
|
|
|
|
|
(xg_reverse_shift_count): Likewise.
|
|
|
|
|
|
* config/xtensa-relax.c (enter_opname_n): Likewise.
|
|
|
|
|
|
(split_string): Likewise.
|
|
|
|
|
|
* dwarf2dbg.c (get_filenum): Likewise.
|
|
|
|
|
|
(process_entries): Likewise.
|
|
|
|
|
|
* expr.c (operand): Likewise.
|
|
|
|
|
|
* itbl-ops.c (alloc_entry): Likewise.
|
|
|
|
|
|
* listing.c (listing_message): Likewise.
|
|
|
|
|
|
(listing_title): Likewise.
|
|
|
|
|
|
* macro.c (check_macro): Likewise.
|
|
|
|
|
|
* stabs.c (s_xstab): Likewise.
|
|
|
|
|
|
* symbols.c (symbol_relc_make_expr): Likewise.
|
|
|
|
|
|
* write.c (compress_debug): Likewise.
|
|
|
|
|
|
|
2016-05-13 00:19:44 +08:00
|
|
|
|
2016-05-12 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/20068
|
|
|
|
|
|
* testsuite/gas/arm/pr20068.d: Use correct regexp syntax.
|
|
|
|
|
|
|
2016-05-12 01:04:03 +08:00
|
|
|
|
2016-05-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/20068
|
|
|
|
|
|
* testsuite/gas/arm/pr20068.d: Adjust expected output to allow for
|
|
|
|
|
|
big endian ARM configurations.
|
|
|
|
|
|
|
2014-11-26 19:15:01 +08:00
|
|
|
|
2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
|
|
|
|
|
|
Matthew Fortune <matthew.fortune@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (options): Add OPTION_DSPR3 and
|
|
|
|
|
|
OPTION_NO_DSPR3.
|
|
|
|
|
|
(md_longopts): Likewise.
|
|
|
|
|
|
(md_show_usage): Add help for -mdspr3 and -mno-dspr3.
|
|
|
|
|
|
(mips_ases): Define availability for DSPr3.
|
|
|
|
|
|
(mips_ase_groups): Add ASE_DSPR3 to the DSP group.
|
|
|
|
|
|
(mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3.
|
|
|
|
|
|
* doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2
|
|
|
|
|
|
formatting.
|
|
|
|
|
|
* doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and
|
|
|
|
|
|
.set nodspr3. Fix -mdspr2 formatting.
|
|
|
|
|
|
* testsuite/gas/mips/mips32-dspr3.d: New file.
|
|
|
|
|
|
* testsuite/gas/mips/mips32-dspr3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run mips32-dspr3 test.
|
|
|
|
|
|
|
2016-05-11 19:51:04 +08:00
|
|
|
|
2016-05-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/20068
|
|
|
|
|
|
* config/tc-arm.c (add_to_lit_pool): Ensure that the padding added
|
|
|
|
|
|
to the pool uses O_constant.
|
|
|
|
|
|
* testsuite/gas/arm/pr20068.s: New test.
|
|
|
|
|
|
* testsuite/gas/arm/pr20068.d: Test driver.
|
|
|
|
|
|
|
2016-05-11 16:04:17 +08:00
|
|
|
|
2016-05-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
2016-05-11 16:06:58 +08:00
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-base.d: Skip for non-ELF ARM targets.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
|
2016-05-11 16:04:17 +08:00
|
|
|
|
|
|
|
|
|
|
2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run RDPID tests.
|
|
|
|
|
|
* testsuite/gas/i386/prefix.d: Adjust.
|
|
|
|
|
|
* testsuite/gas/i386/rdpid.s: New test.
|
|
|
|
|
|
* testsuite/gas/i386/rdpid.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/rdpid-intel.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-rdpid.s: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-rdpid.d: Ditto.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-rdpid-intel.d: Ditto.
|
|
|
|
|
|
|
2016-05-11 02:35:52 +08:00
|
|
|
|
2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add RDPID.
|
|
|
|
|
|
* doc/c-i386.texi: Document RDPID.
|
|
|
|
|
|
|
2016-05-10 23:14:23 +08:00
|
|
|
|
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to
|
|
|
|
|
|
set branch type of a symbol.
|
|
|
|
|
|
|
2016-05-10 22:15:15 +08:00
|
|
|
|
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Document ARMv8-M and ARMv8-M Security and DSP Extensions.
|
|
|
|
|
|
* config/tc-arm.c (arm_ext_dsp): New feature for Thumb DSP
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
(arm_extensions): Add dsp extension for ARMv8-M Mainline.
|
|
|
|
|
|
(aeabi_set_public_attributes): Memorize the feature bits of the
|
|
|
|
|
|
architecture selected for Tag_CPU_arch. Use it to set
|
|
|
|
|
|
Tag_DSP_extension to 1 for ARMv8-M Mainline with DSP extension.
|
|
|
|
|
|
(arm_convert_symbolic_attribute): Define Tag_DSP_extension.
|
|
|
|
|
|
* testsuite/gas/arm/arch7em-bad.d: Rename to ...
|
|
|
|
|
|
* testsuite/gas/arm/arch7em-bad-1.d: This.
|
|
|
|
|
|
* testsuite/gas/arm/arch7em-bad-2.d: New file.
|
|
|
|
|
|
* testsuite/gas/arm/arch7em-bad-3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/attr-march-armv8m.main.dsp.d: Likewise.
|
|
|
|
|
|
|
2016-05-10 22:06:41 +08:00
|
|
|
|
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (struct arm_option_extension_value_table): Make
|
|
|
|
|
|
allowed_archs an array with 2 entries.
|
|
|
|
|
|
(ARM_EXT_OPT): Adapt to only fill the first entry of allowed_archs.
|
|
|
|
|
|
(ARM_EXT_OPT2): New macro filling the two entries of allowed_archs.
|
|
|
|
|
|
(arm_extensions): Use separate entries in allowed_archs when several
|
|
|
|
|
|
archs are allowed to use an extension and change ARCH_ANY in
|
|
|
|
|
|
ARM_ARCH_NONE in allowed_archs.
|
|
|
|
|
|
(arm_parse_extension): Check that, for each allowed_archs entry, all
|
|
|
|
|
|
bits are set in the current architecture, ignoring ARM_ANY entries.
|
|
|
|
|
|
(s_arm_arch_extension): Likewise.
|
|
|
|
|
|
|
2016-05-10 22:01:53 +08:00
|
|
|
|
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
|
|
|
|
|
|
(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
|
|
|
|
|
|
(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
|
|
|
|
|
|
shared with a non M profile architecture.
|
|
|
|
|
|
(do_rn): New function.
|
|
|
|
|
|
(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
|
|
|
|
|
|
than arm_ext_v8m.
|
|
|
|
|
|
(v7m_psrs): Add ARMv8-M security extensions new special registers.
|
|
|
|
|
|
(insns): Add ARMv8-M Security Extensions instructions.
|
|
|
|
|
|
(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
|
|
|
|
|
|
arm_ext_v8m_m to decide the profile and the Thumb ISA.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse.s: New file.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/any-cmse.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/any-cmse-main.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
|
|
|
|
|
|
|
2016-05-09 19:09:53 +08:00
|
|
|
|
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
|
|
|
|
|
|
* testsuite/gas/sparc/sparc5vis4.d: Likewise.
|
|
|
|
|
|
|
2016-05-06 20:36:07 +08:00
|
|
|
|
2016-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (fpu_arch_vfp_v1): Mark with ATTRIBUTE_UNUSED.
|
|
|
|
|
|
(fpu_arch_vfp_v3): Likewise.
|
|
|
|
|
|
(fpu_arch_neon_v1): Likewise.
|
|
|
|
|
|
(arm_arch_full): Likewise.
|
|
|
|
|
|
(parse_neon_el_struct_list): Initialize fields of firsttype.
|
|
|
|
|
|
|
2016-05-03 19:44:13 +08:00
|
|
|
|
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP.
|
|
|
|
|
|
(arc_extinsn): Handle new introduced syntax.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn1op.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn1op.s: Likewise.
|
|
|
|
|
|
* doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP.
|
|
|
|
|
|
|
2016-05-03 17:56:30 +08:00
|
|
|
|
2016-05-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/lns/lns.exp: Add avr to list of targets using
|
|
|
|
|
|
DW_LNS_fixed_advance_pc.
|
|
|
|
|
|
|
2016-04-27 14:12:50 +08:00
|
|
|
|
2016-04-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* as.h (inline, __PTR_TO_INT, __INT_TO_PTR): Don't define.
|
|
|
|
|
|
(xmemdup0): New inline function.
|
|
|
|
|
|
|
2016-04-22 08:04:52 +08:00
|
|
|
|
2016-04-22 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (code_option_type): New enum.
|
|
|
|
|
|
(parse_code_option): Return status indicating option type.
|
|
|
|
|
|
(s_mipsset): Update `parse_code_option' call site accordingly.
|
|
|
|
|
|
Always set register sizes from the ISA with ISA overrides.
|
|
|
|
|
|
(s_module): Update `parse_code_option' call site.
|
|
|
|
|
|
* testsuite/gas/mips/isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/micromips@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips1@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips2@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r2@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r3@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r5@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r6@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips64r2@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips64r3@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips64r5@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/mips64r6@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/r3000@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/r3900@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/r5900@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/octeon@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/octeon3@isa-override-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/mips1@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/mips2@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r2@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r3@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r5@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r6@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/r3000@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/r3900@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/octeon3@isa-override-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/octeon3@isa-override-1.l: New stderr
|
|
|
|
|
|
output.
|
|
|
|
|
|
* testsuite/gas/mips/isa-override-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/r5900@isa-override-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips1@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips2@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips32@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r2@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r3@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r5@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips32r6@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/r3000@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/r3900@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/octeon3@isa-override-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-04-14 06:30:46 +08:00
|
|
|
|
2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen.c: Likewise.
|
|
|
|
|
|
* config/tc-bfin.c: Likewise.
|
|
|
|
|
|
* config/tc-ia64.c: Likewise.
|
|
|
|
|
|
* config/tc-mep.c: Likewise.
|
|
|
|
|
|
* config/tc-metag.c: Likewise.
|
|
|
|
|
|
* config/tc-nios2.c: Likewise.
|
|
|
|
|
|
* config/tc-rl78.c: Likewise.
|
|
|
|
|
|
|
2016-04-20 02:02:27 +08:00
|
|
|
|
2016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-arc.texi (ARC Options): Add nps400 to list of valus for
|
|
|
|
|
|
-mcpu. Add cross reference to .cpu directive from -mcpu option.
|
|
|
|
|
|
(ARC Directives): Add NPS400 to .cpu directive list.
|
|
|
|
|
|
|
2016-04-20 16:31:49 +08:00
|
|
|
|
2016-04-20 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_features): Add "ras".
|
|
|
|
|
|
* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
|
|
|
|
|
|
* testsuite/gas/aarch64/armv8-ras-1.d: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/armv8-ras-1.s: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/illegal-ras-1.d: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/illegal-ras-1.s: New.
|
|
|
|
|
|
|
opcodes/arc: Add yet more nps instructions
Add some more arc/nps400 instructions and the associated operands.
There's also a test added into the assembler.
gas/ChangeLog:
* testsuite/gas/arc/nps400-6.d: New file.
* testsuite/gas/arc/nps400-6.s: New file.
include/ChangeLog:
* opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, and qcmp
instructions.
* arc-opc.c (insert_nps_bitop_size): Delete.
(extract_nps_bitop_size): Delete.
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
(extract_nps_qcmp_m3): Define.
(extract_nps_qcmp_m2): Define.
(extract_nps_qcmp_m1): Define.
(arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
(arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
(arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
NPS_QCMP_M3.
2016-04-02 02:51:50 +08:00
|
|
|
|
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-6.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-6.s: New file.
|
|
|
|
|
|
|
2016-04-01 02:51:14 +08:00
|
|
|
|
2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-4.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-4.s: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-5.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-5.s: New file.
|
|
|
|
|
|
|
2016-04-19 07:46:09 +08:00
|
|
|
|
2016-04-19 Martin Galvan <martin.galvan@tallertechnologies.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (.cfi_remember_state, .cfi_restore_state): Improve
|
|
|
|
|
|
documentation.
|
|
|
|
|
|
|
2016-04-18 06:17:44 +08:00
|
|
|
|
2016-04-17 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
Revert prevous change.
|
|
|
|
|
|
* config/tc-arc.c (arc_option): Make .cpu directive
|
|
|
|
|
|
case-sensitive again.
|
|
|
|
|
|
|
2016-04-16 23:21:32 +08:00
|
|
|
|
2016-04-16 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (arc_option): Make .cpu directive
|
|
|
|
|
|
case-insensitive.
|
|
|
|
|
|
|
2016-04-16 23:19:40 +08:00
|
|
|
|
2016-04-16 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (arc_option): Allow NPS400 in .cpu directive.
|
|
|
|
|
|
|
2016-04-13 17:03:22 +08:00
|
|
|
|
2016-04-15 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_begin): Remove useless assignment.
|
|
|
|
|
|
|
2016-04-16 07:20:02 +08:00
|
|
|
|
2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.in: Regenerated with automake 1.11.6.
|
|
|
|
|
|
* aclocal.m4: Likewise.
|
|
|
|
|
|
* doc/Makefile.in: Likewise.
|
|
|
|
|
|
|
2016-04-15 22:07:30 +08:00
|
|
|
|
2016-04-15 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (toc_reloc_types): Wrap in #ifdef OBJ_ELF
|
|
|
|
|
|
|
2016-04-13 16:15:10 +08:00
|
|
|
|
2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nios2.c (nios2_as_options): Make file static.
|
|
|
|
|
|
* config/tc-ppc.c (toc_reloc_ypes): Likewise.
|
|
|
|
|
|
* config/tc-sparc.c (native_op_table): Likewise.
|
|
|
|
|
|
|
2016-04-12 22:02:58 +08:00
|
|
|
|
2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m32c.c (M32C_Macros): Remove.
|
|
|
|
|
|
* config/tc-msp430.c (option_numbers): Likewise.
|
|
|
|
|
|
|
arc/nps400 : New cmem instructions and associated relocation
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".
Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.
There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.
bfd/ChangeLog:
* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c: Add 'opcode/arc.h' include.
(struct arc_relocation_data): Add symbol_name.
(arc_special_overflow_checks): New function.
(arc_do_relocation): Use arc_special_overflow_checks, reindent as
required, add an extra comment.
(elf_arc_relocate_section): Setup symbol_name in reloc_data.
gas/ChangeLog:
* testsuite/gas/arc/nps400-3.d: New file.
* testsuite/gas/arc/nps400-3.s: New file.
include/ChangeLog:
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
ld/ChangeLog:
* testsuite/ld-arc/arc.exp: New file.
* testsuite/ld-arc/nps-1.s: New file.
* testsuite/ld-arc/nps-1a.d: New file.
* testsuite/ld-arc/nps-1b.d: New file.
* testsuite/ld-arc/nps-1b.err: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
instructions.
* arc-opc.c (insert_nps_cmem_uimm16): New function.
(extract_nps_cmem_uimm16): New function.
(arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-03-30 07:02:19 +08:00
|
|
|
|
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-3.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-3.s: New file.
|
|
|
|
|
|
|
2016-04-08 05:56:44 +08:00
|
|
|
|
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/add_s-err.s: Update target pattern.
|
|
|
|
|
|
* testsuite/gas/arc/warn.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run test for arc.
|
|
|
|
|
|
|
2016-04-14 19:04:09 +08:00
|
|
|
|
2016-04-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/19938
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string
|
|
|
|
|
|
sections possibly having the SHF_STRINGS flag bit set.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-unwind.d: Likewise.
|
|
|
|
|
|
|
2016-04-12 20:51:57 +08:00
|
|
|
|
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (mach_type_specified_p): Change type to
|
|
|
|
|
|
bfd_boolean.
|
|
|
|
|
|
(arc_option): Set private flags when parsing cpu pseudo-op.
|
|
|
|
|
|
(md_parse_option): Set mach_type_specified_p to TRUE.
|
|
|
|
|
|
|
2016-04-13 22:10:48 +08:00
|
|
|
|
2016-04-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/19937
|
|
|
|
|
|
* testsuite/gas/v850/pr19937.s: New test.
|
|
|
|
|
|
* testsuite/gas/v850/pr19937.d: New test control file.
|
|
|
|
|
|
* testsuite/gas/v850/basic.exp: Run the new test.
|
|
|
|
|
|
|
2016-04-09 18:59:36 +08:00
|
|
|
|
2016-04-13 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
Andrew Bennett <andrew.bennett@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (relaxed_branch_length): Use the long
|
|
|
|
|
|
sequence where the target is a weak symbol.
|
|
|
|
|
|
(relaxed_micromips_32bit_branch_length): Likewise.
|
|
|
|
|
|
(relaxed_micromips_16bit_branch_length): Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak-5.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/branch-weak.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-04-09 07:20:35 +08:00
|
|
|
|
2016-04-13 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (relaxed_branch_length): Use the long
|
|
|
|
|
|
sequence where the distance cannot be determined.
|
|
|
|
|
|
(relaxed_micromips_32bit_branch_length): Likewise.
|
|
|
|
|
|
* testsuite/gas/mips/branch-extern-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-extern-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-extern-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-extern-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-extern.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/branch-extern.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/branch-section-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-section-2.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-section-3.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-section-4.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/branch-section.l: New stderr output.
|
|
|
|
|
|
* testsuite/gas/mips/branch-section.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-04-06 22:08:04 +08:00
|
|
|
|
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/textauxregister.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/textauxregister.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textcondcode.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textcondcode.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textcoreregister.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textcoreregister.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textpseudoop.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textpseudoop.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/ld2.d: Update test.
|
|
|
|
|
|
* testsuite/gas/arc/st.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/taux.d: Likewise.
|
|
|
|
|
|
* doc/c-arc.texi (ARC Directives): Add .extCondCode,
|
|
|
|
|
|
.extCoreRegister and .extAuxRegister documentation.
|
|
|
|
|
|
* config/tc-arc.c (arc_extcorereg): New function.
|
|
|
|
|
|
(md_pseudo_table): Add .extCondCode, .extCoreRegister and
|
|
|
|
|
|
.extAuxRegister pseudo-ops.
|
|
|
|
|
|
(extRegister_t): New type.
|
|
|
|
|
|
(ext_condcode, arc_aux_hash): New global variable.
|
|
|
|
|
|
(find_opcode_match): Check for extensions.
|
|
|
|
|
|
(preprocess_operands): Likewise.
|
|
|
|
|
|
(md_begin): Add aux registers in a hash.
|
|
|
|
|
|
(assemble_insn): Update use arc_flags member.
|
|
|
|
|
|
(tokenize_extregister): New function.
|
|
|
|
|
|
(create_extcore_section): Likewise.
|
|
|
|
|
|
* config/tc-arc.h (arc_flags): Delete code, add flgp.
|
|
|
|
|
|
|
2016-04-06 22:47:56 +08:00
|
|
|
|
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/noargs_a7.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/noargs_a7.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/noargs_hs.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/noargs_hs.s: Likewise.
|
|
|
|
|
|
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 22:03:53 +08:00
|
|
|
|
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/textinsn-errors.d: New File.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn-errors.err: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn-errors.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn2op.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn2op.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn2op01.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn2op01.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn3op.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/textinsn3op.s: Likewise.
|
|
|
|
|
|
* doc/c-arc.texi (ARC Directives): Add .extInstruction
|
|
|
|
|
|
documentation.
|
|
|
|
|
|
* config/tc-arc.c (arcext_section): New variable.
|
|
|
|
|
|
(arc_extinsn): New function.
|
|
|
|
|
|
(md_pseudo_table): Add .extInstruction pseudo op.
|
|
|
|
|
|
(attributes_t): New type.
|
|
|
|
|
|
(suffixclass, syntaxclass, syntaxclassmod): New constant
|
|
|
|
|
|
structures.
|
|
|
|
|
|
(find_opcode_match): Remove arc_num_opcodes.
|
|
|
|
|
|
(md_begin): Likewise.
|
|
|
|
|
|
(tokenize_extinsn): New function.
|
|
|
|
|
|
(arc_set_ext_seg): Likewise.
|
|
|
|
|
|
(create_extinst_section): Likewise.
|
|
|
|
|
|
|
2016-03-31 18:40:13 +08:00
|
|
|
|
2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (preprocess_operands): Mark AUX symbol.
|
|
|
|
|
|
(arc_adjust_symtab): New function.
|
|
|
|
|
|
* config/tc-arc.h (ARC_FLAG_AUX): Define.
|
|
|
|
|
|
(obj_adjust_symtab): Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/taux.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/taux.s: Likewise.
|
|
|
|
|
|
|
2016-04-10 04:35:50 +08:00
|
|
|
|
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (s_option): Sanitize `.option picX'
|
|
|
|
|
|
pseudo-op.
|
|
|
|
|
|
* testsuite/gas/mips/option-pic-1.d: New test.
|
|
|
|
|
|
* testsuite/gas/mips/option-pic-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/option-pic-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/option-pic-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-04-10 04:23:40 +08:00
|
|
|
|
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (s_option): Reject `.option picX' if VxWorks
|
|
|
|
|
|
PIC.
|
|
|
|
|
|
* testsuite/gas/mips/option-pic-vxworks-1.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/option-pic-vxworks-2.l: New list test.
|
|
|
|
|
|
* testsuite/gas/mips/option-pic-vxworks-1.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/option-pic-vxworks-2.s: New test source.
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run the new tests.
|
|
|
|
|
|
|
2016-04-09 20:27:30 +08:00
|
|
|
|
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (can_swap_branch_p): Correct call formatting.
|
|
|
|
|
|
|
2016-04-09 20:22:54 +08:00
|
|
|
|
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* messages.c (as_bad): Fix a typo in description.
|
|
|
|
|
|
|
2016-04-09 20:19:00 +08:00
|
|
|
|
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_check_options): Unify messages.
|
|
|
|
|
|
|
2016-04-09 19:55:09 +08:00
|
|
|
|
2016-04-09 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_check_options): Use `opts->isa'
|
|
|
|
|
|
consistently.
|
|
|
|
|
|
|
2016-04-08 17:36:49 +08:00
|
|
|
|
2016-04-08 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/19910
|
|
|
|
|
|
* testsuite/gas/sparc/pr19910-1.d: Adjust regexps to work with
|
|
|
|
|
|
COFF and AOUT sparc targets.
|
|
|
|
|
|
|
2016-03-29 06:05:09 +08:00
|
|
|
|
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.h (MAX_FLAG_NAME_LENGTH): Increase to 7.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-2.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-2.s: New file.
|
|
|
|
|
|
|
2016-03-29 00:08:29 +08:00
|
|
|
|
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (struct arc_opcode_hash_entry_iterator): New
|
|
|
|
|
|
structure.
|
|
|
|
|
|
(arc_opcode_hash_entry_iterator_init): New function.
|
|
|
|
|
|
(arc_opcode_hash_entry_iterator_next): New function.
|
|
|
|
|
|
(find_opcode_match): Iterate over all arc_opcode entries
|
|
|
|
|
|
referenced by the arc_opcode_hash_entry passed in as a parameter.
|
|
|
|
|
|
|
2016-03-28 23:04:58 +08:00
|
|
|
|
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (arc_find_opcode): Now returns
|
|
|
|
|
|
arc_opcode_hash_entry pointer.
|
|
|
|
|
|
(find_opcode_match): Update argument type, extract arc_opcode from
|
|
|
|
|
|
incoming arc_opcode_hash_entry.
|
|
|
|
|
|
(find_special_case_pseudo): Update return type.
|
|
|
|
|
|
(find_special_case_flag): Update return type.
|
|
|
|
|
|
(find_special_case): Update return type.
|
|
|
|
|
|
(assemble_tokens): Lookup arc_opcode_hash_entry based on
|
|
|
|
|
|
instruction mnemonic, then use find_opcode_match to identify
|
|
|
|
|
|
specific arc_opcode.
|
|
|
|
|
|
|
gas/arc: Modify structure used to hold opcodes
The arc assembler builds a hash table to hold references to arc_opcode
entries in the arc_opcodes table. This hash assumes that each mnemonic
will always appear in a contiguous blocks within the arc_opcodes table;
all ADD instruction will be together, all AND instructions will likewise
be together and so on.
The problem with this is that as different variations of arc are added,
then it is often more convenient to split instructions apart, so all the
base ADD instructions are together, but, variants of ADD specific to one
variation of arc are grouped with other instructions specific to that
arc variant. The current data structures don't support splitting the
instructions in this way.
This commit is a first step towards addressing this limitation. In this
commit the hash table that currently holds arc_opcode pointers directly,
instead holds a pointer to a new, intermediate, data structure. This
new data structure holds the pointer to the arc_opcode. In this way, we
can, in the future support having the intermediate structure hold
multiple pointers to different arc_opcode groups.
There should be no visible functional change after this commit.
gas/ChangeLog:
* config/tc-arc.c (struct arc_opcode_hash_entry): New structure.
(arc_find_opcode): New function.
(find_special_case_pseudo): Use arc_find_opcode.
(find_special_case_flag): Likewise.
(assemble_tokens): Likewise.
(md_begin): Build hash using struct arc_opcode_hash_entry.
2016-03-28 21:27:43 +08:00
|
|
|
|
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (struct arc_opcode_hash_entry): New structure.
|
|
|
|
|
|
(arc_find_opcode): New function.
|
|
|
|
|
|
(find_special_case_pseudo): Use arc_find_opcode.
|
|
|
|
|
|
(find_special_case_flag): Likewise.
|
|
|
|
|
|
(assemble_tokens): Likewise.
|
|
|
|
|
|
(md_begin): Build hash using struct arc_opcode_hash_entry.
|
|
|
|
|
|
|
2016-04-07 20:01:17 +08:00
|
|
|
|
2016-04-07 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* config/tc-arc.c (arc_option): Prepare string for automatic
|
|
|
|
|
|
translation.
|
|
|
|
|
|
(declare_register): Likewise.
|
2016-04-07 20:01:17 +08:00
|
|
|
|
|
2016-04-07 20:29:50 +08:00
|
|
|
|
2016-04-06 James Greenhalgh <james.greenhalgh@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-aarch64.texi (Architecture Extensions): Add entry for LSE.
|
|
|
|
|
|
Correct entry for RDMA. Alpha sort entries.
|
|
|
|
|
|
|
2016-03-29 05:51:12 +08:00
|
|
|
|
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (tokenize_flags): Allow greater range of
|
|
|
|
|
|
characters into flag names.
|
|
|
|
|
|
|
2016-03-28 22:49:25 +08:00
|
|
|
|
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (find_opcode_match): Handle O_symbol case, add
|
|
|
|
|
|
new de_fault label.
|
|
|
|
|
|
(preprocess_operands): Delete.
|
|
|
|
|
|
(assemble_tokens): Remove call to preprocess_operands.
|
|
|
|
|
|
|
2016-04-07 19:34:06 +08:00
|
|
|
|
2016-04-07 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19910
|
|
|
|
|
|
* config/tc-sparc.c (sparc_ip): Report an error if the expression
|
|
|
|
|
|
inside a %-macro could not be fully parsed.
|
|
|
|
|
|
* expr.c (integer_constant): Accept and ignore U suffixes to
|
|
|
|
|
|
integers.
|
|
|
|
|
|
(operand): When a missing closing parenthesis is encountered,
|
|
|
|
|
|
report the character that was found instead.
|
|
|
|
|
|
* testsuite/gas/mips/tls-ill.l: Update expected error message.
|
|
|
|
|
|
* testsuite/gas/sparc/pr19910-1.d: New test driver.
|
|
|
|
|
|
* testsuite/gas/sparc/pr19910-1.s: New test.
|
|
|
|
|
|
* testsuite/gas/sparc/pr19910-2.l: Expected error output.
|
|
|
|
|
|
* testsuite/gas/sparc/pr19910-2.s: New test.
|
|
|
|
|
|
* testsuite/gas/sparc/sparc.exp: Run the new tests.
|
|
|
|
|
|
|
2016-04-06 22:57:19 +08:00
|
|
|
|
2016-04-06 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-msp430.c (msp430_operands): Check for a NOP preceding
|
|
|
|
|
|
an EINT instruction. Warn/fix as necessary.
|
|
|
|
|
|
* testsuite/gas/msp430/bad.s: Add test of EINT without preceding NOP.
|
|
|
|
|
|
* testsuite/gas/msp430/bad.l: Update expected messages.
|
|
|
|
|
|
|
arc/nps400: Add additional instructions
Adds the movbi, decode1, fbset, fbclear, encode0, encode1, rflt, crc16,
and crc32 instructions for the nps400 arc machine type.
gas/ChangeLog:
* testsuite/gas/arc/nps400-1.d: Update expected results.
* testsuite/gas/arc/nps400-1.s: Additional test cases.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
encode1, rflt, crc16, and crc32 instructions.
* arc-opc.c (arc_flag_operands): Add F_NPS_R.
(arc_flag_classes): Add C_NPS_R.
(insert_nps_bitop_size_2b): New function.
(extract_nps_bitop_size_2b): Likewise.
(insert_nps_bitop_uimm8): Likewise.
(extract_nps_bitop_uimm8): Likewise.
(arc_operands): Add new operand entries.
2016-03-22 02:49:34 +08:00
|
|
|
|
2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-1.d: Update expected results.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-1.s: Additional test cases.
|
|
|
|
|
|
|
2016-04-05 23:37:29 +08:00
|
|
|
|
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* config/tc-arc.c (is_code_density_p): Compare directly the
|
|
|
|
|
|
subclass field.
|
|
|
|
|
|
(is_spfp_p, is_dpfp_p, is_spfp_p): Define.
|
|
|
|
|
|
(check_cpu_feature): New function.
|
|
|
|
|
|
(find_opcode_match): Use check_cpu_feature function.
|
|
|
|
|
|
(preprocess_operands): Likewise.
|
|
|
|
|
|
(md_parse_option): Use mfpuda, mdpfp, mspfp options.
|
|
|
|
|
|
* testsuite/gas/arc/tdpfp.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/tfpuda.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/tfpx.s: Likewise.
|
2016-04-05 23:37:29 +08:00
|
|
|
|
|
2016-04-05 22:54:00 +08:00
|
|
|
|
2016-04-05 Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd.s: New tests.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results.
|
|
|
|
|
|
* testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source.
|
|
|
|
|
|
* testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase.
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise
|
|
|
|
|
|
for Thumb.
|
2016-04-05 22:54:00 +08:00
|
|
|
|
* testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results.
|
|
|
|
|
|
|
2016-04-05 22:22:19 +08:00
|
|
|
|
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* config/tc-arc.c (assemble_insn): Prohibit pc-rel relocations for
|
2016-04-05 22:22:19 +08:00
|
|
|
|
JUMP instructions type.
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* testsuite/gas/arc/relocs-errors.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/relocs-errors.err: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relocs-errors.s: Likewise.
|
2016-04-05 22:22:19 +08:00
|
|
|
|
|
2016-04-15 20:59:16 +08:00
|
|
|
|
2016-04-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19909
|
|
|
|
|
|
* config/tc-i386.c (check_VecOperands): Try vec_disp8 encoding
|
|
|
|
|
|
only if i.disp_encoding != disp_encoding_32bit.
|
|
|
|
|
|
* gas/testsuite/gas/i386/disp32.s: Add tests for vmovdqu64.d32.
|
|
|
|
|
|
* gas/testsuite/gas/i386/x86-64-disp32.s: Likewise.
|
|
|
|
|
|
* gas/testsuite/gas/i386/disp32.d: Updated.
|
|
|
|
|
|
* gas/testsuite/gas/i386/x86-64-disp32.d: Likewise.
|
|
|
|
|
|
|
2016-04-05 11:45:30 +08:00
|
|
|
|
2016-04-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19498
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run pr19498.
|
|
|
|
|
|
* testsuite/gas/i386/pr19498.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/pr19498.s: Likewise.
|
|
|
|
|
|
|
2016-04-02 01:35:29 +08:00
|
|
|
|
2016-04-04 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.h: Include 'opcode/arc.h'.
|
|
|
|
|
|
(MAX_INSN_ARGS): Delete.
|
|
|
|
|
|
(MAX_INSN_FLGS): Delete.
|
|
|
|
|
|
|
2016-04-04 14:49:27 +08:00
|
|
|
|
2016-04-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 19498
|
|
|
|
|
|
* symbols.c (resolve_symbol_value): Clear sy_resolving on exit
|
|
|
|
|
|
from function on all paths that set sy_resolving.
|
|
|
|
|
|
|
2016-04-01 21:26:30 +08:00
|
|
|
|
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* app.c (app_push): use XNEW macro.
|
|
|
|
|
|
* as.c: Likewise.
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_change_section): Likewise.
|
|
|
|
|
|
(elf_copy_symbol_attributes): Likewise.
|
|
|
|
|
|
(obj_elf_size): Likewise.
|
|
|
|
|
|
(build_group_lists): Likewise.
|
|
|
|
|
|
* config/tc-aarch64.c (add_operand_error_record): Likewise.
|
|
|
|
|
|
(md_assemble): Likewise.
|
|
|
|
|
|
(tc_gen_reloc): Likewise.
|
|
|
|
|
|
(get_upper_str): Likewise.
|
|
|
|
|
|
(aarch64_parse_features): Likewise.
|
|
|
|
|
|
* config/tc-arm.c (insert_reg_alias): Likewise.
|
|
|
|
|
|
(insert_neon_reg_alias): Likewise.
|
|
|
|
|
|
(find_or_make_literal_pool): Likewise.
|
|
|
|
|
|
(s_arm_elf_cons): Likewise.
|
|
|
|
|
|
(add_unwind_opcode): Likewise.
|
|
|
|
|
|
(arm_parse_extension): Likewise.
|
|
|
|
|
|
* config/tc-avr.c (create_record_for_frag): Likewise.
|
|
|
|
|
|
* config/tc-crx.c: Likewise.
|
|
|
|
|
|
* config/tc-d30v.c: Likewise.
|
|
|
|
|
|
* config/tc-dlx.c (s_proc): Likewise.
|
|
|
|
|
|
* config/tc-ft32.c: Likewise.
|
|
|
|
|
|
* config/tc-h8300.c: Likewise.
|
|
|
|
|
|
* config/tc-hppa.c (pa_proc): Likewise.
|
|
|
|
|
|
(create_new_space): Likewise.
|
|
|
|
|
|
(create_new_subspace): Likewise.
|
|
|
|
|
|
* config/tc-i860.c: Likewise.
|
|
|
|
|
|
* config/tc-i960.c: Likewise.
|
|
|
|
|
|
* config/tc-ia64.c: Likewise.
|
|
|
|
|
|
* config/tc-iq2000.c (iq2000_add_macro): Likewise.
|
|
|
|
|
|
(iq2000_record_hi16): Likewise.
|
|
|
|
|
|
* config/tc-m32c.c (m32c_indirect_operand): Likewise.
|
|
|
|
|
|
* config/tc-m32r.c (debug_sym): Likewise.
|
|
|
|
|
|
(m32r_record_hi16): Likewise.
|
|
|
|
|
|
* config/tc-m68k.c (m68k_ip): Likewise.
|
|
|
|
|
|
(md_begin): Likewise.
|
|
|
|
|
|
* config/tc-mcore.c: Likewise.
|
|
|
|
|
|
* config/tc-microblaze.c (check_got): Likewise.
|
|
|
|
|
|
* config/tc-mips.c (append_insn): Likewise.
|
|
|
|
|
|
(s_mipsset): Likewise.
|
|
|
|
|
|
(mips_record_label): Likewise.
|
|
|
|
|
|
(s_mips_end): Likewise.
|
|
|
|
|
|
* config/tc-mmix.c (mmix_frob_file): Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10300.c: Likewise.
|
|
|
|
|
|
* config/tc-moxie.c: Likewise.
|
|
|
|
|
|
* config/tc-msp430.c: Likewise.
|
|
|
|
|
|
* config/tc-nds32.c (nds32_elf_save_pseudo_pattern): Likewise.
|
|
|
|
|
|
* config/tc-ns32k.c: Likewise.
|
|
|
|
|
|
* config/tc-or1k.c: Likewise.
|
|
|
|
|
|
* config/tc-pdp11.c: Likewise.
|
|
|
|
|
|
* config/tc-pj.c (fake_opcode): Likewise.
|
|
|
|
|
|
* config/tc-ppc.c (ppc_apuinfo_section_add): Likewise.
|
|
|
|
|
|
(ppc_macro): Likewise.
|
|
|
|
|
|
(ppc_dwsect): Likewise.
|
|
|
|
|
|
(ppc_machine): Likewise.
|
|
|
|
|
|
* config/tc-rl78.c (rl78_frag_init): Likewise.
|
|
|
|
|
|
* config/tc-rx.c (rx_frag_init): Likewise.
|
|
|
|
|
|
* config/tc-s390.c (s390_lit_suffix): Likewise.
|
|
|
|
|
|
(s390_machine): Likewise.
|
|
|
|
|
|
(s390_machinemode): Likewise.
|
|
|
|
|
|
* config/tc-score.c (s3_insert_reg): Likewise.
|
|
|
|
|
|
(s3_gen_reloc): Likewise.
|
|
|
|
|
|
* config/tc-score7.c (s7_insert_reg): Likewise.
|
|
|
|
|
|
(s7_gen_reloc): Likewise.
|
|
|
|
|
|
* config/tc-tic30.c (tic30_operand): Likewise.
|
|
|
|
|
|
* config/tc-tic4x.c (tic4x_inst_make): Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c (stag_add_field): Likewise.
|
|
|
|
|
|
(tic54x_struct): Likewise.
|
|
|
|
|
|
(tic54x_space): Likewise.
|
|
|
|
|
|
(tic54x_field): Likewise.
|
|
|
|
|
|
(tic54x_mlib): Likewise.
|
|
|
|
|
|
(subsym_substitute): Likewise.
|
|
|
|
|
|
* config/tc-tic6x.c (tic6x_frob_label): Likewise.
|
|
|
|
|
|
* config/tc-vax.c: Likewise.
|
|
|
|
|
|
* config/tc-xc16x.c: Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_add_insn_label): Likewise.
|
|
|
|
|
|
(directive_push): Likewise.
|
|
|
|
|
|
(xtensa_begin_directive): Likewise.
|
|
|
|
|
|
(tokenize_arguments): Likewise.
|
|
|
|
|
|
(xtensa_add_literal_sym): Likewise.
|
|
|
|
|
|
(new_resource_table): Likewise.
|
|
|
|
|
|
(resize_resource_table): Likewise.
|
|
|
|
|
|
(emit_single_op): Likewise.
|
|
|
|
|
|
(xtensa_create_trampoline_frag): Likewise.
|
|
|
|
|
|
(xtensa_maybe_create_literal_pool_frag): Likewise.
|
|
|
|
|
|
(xtensa_add_config_info): Likewise.
|
|
|
|
|
|
(xtensa_realloc_fixup_cache): Likewise.
|
|
|
|
|
|
(add_subseg_info): Likewise.
|
|
|
|
|
|
(cache_literal_section): Likewise.
|
|
|
|
|
|
(add_xt_block_frags): Likewise.
|
|
|
|
|
|
(add_xt_prop_frags): Likewise.
|
|
|
|
|
|
(init_op_placement_info_table): Likewise.
|
|
|
|
|
|
(build_section_rename): Likewise.
|
|
|
|
|
|
* config/tc-z80.c: Likewise.
|
|
|
|
|
|
* config/tc-z8k.c: Likewise.
|
|
|
|
|
|
* depend.c (register_dependency): Likewise.
|
|
|
|
|
|
* dwarf2dbg.c (get_line_subseg): Likewise.
|
|
|
|
|
|
(dwarf2_gen_line_info_1): Likewise.
|
|
|
|
|
|
(get_filenum): Likewise.
|
|
|
|
|
|
* ecoff.c (allocate_scope): Likewise.
|
|
|
|
|
|
(allocate_vlinks): Likewise.
|
|
|
|
|
|
(allocate_shash): Likewise.
|
|
|
|
|
|
(allocate_thash): Likewise.
|
|
|
|
|
|
(allocate_tag): Likewise.
|
|
|
|
|
|
(allocate_forward): Likewise.
|
|
|
|
|
|
(allocate_thead): Likewise.
|
|
|
|
|
|
(allocate_lineno_list): Likewise.
|
|
|
|
|
|
* expr.c (make_expr_symbol): Likewise.
|
|
|
|
|
|
* hash.c (hash_new_sized): Likewise.
|
|
|
|
|
|
* input-file.c (input_file_push): Likewise.
|
|
|
|
|
|
* listing.c (file_info): Likewise.
|
|
|
|
|
|
(listing_newline): Likewise.
|
|
|
|
|
|
* macro.c (new_formal): Likewise.
|
|
|
|
|
|
(define_macro): Likewise.
|
|
|
|
|
|
* remap.c (add_debug_prefix_map): Likewise.
|
|
|
|
|
|
* symbols.c (symbol_find_noref): Likewise.
|
|
|
|
|
|
(define_dollar_label): Likewise.
|
|
|
|
|
|
(fb_label_instance_inc): Likewise.
|
|
|
|
|
|
(symbol_relc_make_value): Likewise.
|
|
|
|
|
|
|
2016-04-02 21:27:18 +08:00
|
|
|
|
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_vendor_attribute): Use xstrdup.
|
|
|
|
|
|
* config/tc-ppc.c (ppc_frob_file_before_adjust): Likewise.
|
|
|
|
|
|
(ppc_znop): Likewise.
|
|
|
|
|
|
(ppc_pe_section): Likewise.
|
|
|
|
|
|
(ppc_frob_symbol): Likewise.
|
|
|
|
|
|
* config/tc-tic30.c (tic30_operand): Likewise.
|
|
|
|
|
|
* config/tc-tic4x.c (tic4x_sect): Likewise.
|
|
|
|
|
|
(tic4x_usect): Likewise.
|
|
|
|
|
|
|
2016-04-03 04:38:40 +08:00
|
|
|
|
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-alpha.c: Const qualify FLT_CHARS.
|
|
|
|
|
|
* config/atof-ieee.c: Remove declarations of FLT_CHARS and EXP_CHARS.
|
|
|
|
|
|
* config/tc-cris.h: Likewise.
|
|
|
|
|
|
* expr.c: Likewise.
|
|
|
|
|
|
* config/tc-mmix.c (md_atof): Adjust comment.
|
|
|
|
|
|
* config/tc-mmix.h: Stop defining FLT_CHARS and EXP_CHARS as macros.
|
|
|
|
|
|
* tc.h: Declare FLT_CHARS and EXP_CHARS.
|
|
|
|
|
|
|
2016-04-04 07:49:05 +08:00
|
|
|
|
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-score.c (s3_gen_reloc): Add const qualifiers.
|
|
|
|
|
|
* config/tc-score7.c (s7_gen_reloc): Likewise.
|
|
|
|
|
|
|
2016-04-01 07:49:05 +08:00
|
|
|
|
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (do_t_branch): Change the type of reloc to
|
|
|
|
|
|
bfd_reloc_code_real_type.
|
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|
|
2016-04-02 20:22:05 +08:00
|
|
|
|
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
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|
|
|
|
|
|
|
|
|
|
* config/bfin-parse.y (current_inputline): Remove definition.
|
|
|
|
|
|
* config/tc-bfin.c (md_assemble): Simplify use of current_inputline.
|
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|
2016-04-02 19:57:10 +08:00
|
|
|
|
2016-04-03 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
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|
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|
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|
|
* config/tc-avr.c (md_parse_option): Use strcasecmp () to compare
|
|
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|
|
strings.
|
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|
2016-04-02 14:47:26 +08:00
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|
2016-04-02 Alan Modra <amodra@gmail.com>
|
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|
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|
|
PR 19896
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|
* read.c (assign_symbol): Consume rest of line after an error
|
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|
|
rather than continuing to process the line.
|
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|
2016-03-29 05:48:34 +08:00
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|
2016-04-01 Andrew Burgess <andrew.burgess@embecosm.com>
|
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|
|
* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Rename to...
|
|
|
|
|
|
(MAX_FLAG_NAME_LENGTH): ...this.
|
|
|
|
|
|
(struct arc_flags): Update to use MAX_FLAG_NAME_LENGTH.
|
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|
|
* config/tc-arc.c (tokenize_flags): Likewise.
|
|
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|
2016-04-01 20:07:50 +08:00
|
|
|
|
2016-04-01 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
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|
|
* cgen.c (weak_operand_overflow_check): Return const char*.
|
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|
|
|
|
* messages.c (as_internal_value_out_of_range): Formatting.
|
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|
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|
|
(as_warn_value_out_of_range): Consify prefix param.
|
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|
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|
|
(as_bad_value_out_of_range): Likewise.
|
|
|
|
|
|
* read.c (s_errwarn): Constify msg..
|
|
|
|
|
|
(s_float_space, float_cons): ..and err.
|
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|
|
* as.h (as_warn_value_out_of_range, as_bad_value_out_of_range,
|
|
|
|
|
|
ieee_md_atof, vax_md_atof): Update prototypes.
|
|
|
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|
|
* tc.h (md_atof): Update prototype.
|
|
|
|
|
|
* config/atof-ieee.c (ieee_md_atof): Return const char*.
|
|
|
|
|
|
* config/atof-vax.c (vax_md_atof): Likewise.
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_parse_section_letters): Constify bad_msg.
|
|
|
|
|
|
* config/tc-aarch64.c (md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-alpha.c (s_alpha_section_name): Likewise.
|
|
|
|
|
|
(s_alpha_comm): Constify sec_name.
|
|
|
|
|
|
(section_name): Constify.
|
|
|
|
|
|
(s_alpha_section): Consify name..
|
|
|
|
|
|
(alpha_elf_section_letter): ..and ptr_msg param..
|
|
|
|
|
|
(md_atof): ..and return.
|
|
|
|
|
|
* config/tc-alpha.h (alpha_elf_section_letter): Update prototype.
|
|
|
|
|
|
* config/tc-arc.c (md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-arm.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-avr.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-bfin.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-cr16.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-cris.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-crx.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-d10v.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-d30v.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-dlx.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-epiphany.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-fr30.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-frv.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-ft32.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-h8300.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-hppa.c (struct default_subspace_dict): Constify name.
|
|
|
|
|
|
(struct default_space_dict): Likewise.
|
|
|
|
|
|
(create_new_space): Constify name param.
|
|
|
|
|
|
(create_new_subspace): Likewise.
|
|
|
|
|
|
(is_defined_space, is_defined_subspace): Likewise.
|
|
|
|
|
|
(pa_parse_space_stmt): Constify space_name param.
|
|
|
|
|
|
(md_atof): Return const char*.
|
|
|
|
|
|
(pa_spaces_begin): Constify name.
|
|
|
|
|
|
* config/tc-i370.c (md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-i386.c (md_atof): Likewise.
|
|
|
|
|
|
(x86_64_section_letter): Constify ptr_msg param.
|
|
|
|
|
|
* config/tc-i386.h (x86_64_section_letter): Update prototype.
|
|
|
|
|
|
* config/tc-i860.c (struct i860_it): Constify error.
|
|
|
|
|
|
(md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-i960.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-ia64.c (md_atof): Likewise.
|
|
|
|
|
|
(ia64_elf_section_letter): Constify ptr_msg param.
|
|
|
|
|
|
* config/tc-ia64.h (ia64_elf_section_letter): Update prototype.
|
|
|
|
|
|
* config/tc-ip2k.c (md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-iq2000.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-lm32.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-m32c.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-m32r.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-m68hc11.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-m68k.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-mcore.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-mep.c (md_atof): Likewise.
|
|
|
|
|
|
(mep_elf_section_letter): Constify ptr_msg param.
|
|
|
|
|
|
* config/tc-mep.h (mep_elf_section_letter): Update prototype.
|
|
|
|
|
|
* config/tc-metag.c (md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-microblaze.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.h (md_atof): Delete prototype.
|
|
|
|
|
|
* config/tc-mips.c (mips_parse_argument_token): Constify err.
|
|
|
|
|
|
(md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-mmix.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-mn10300.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-moxie.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-msp430.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-mt.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-nds32.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-nios2.c (md_atof): Likewise.
|
|
|
|
|
|
(nios2_elf_section_letter): Constify ptr_msg param.
|
|
|
|
|
|
* config/tc-nios2.h (nios2_elf_section_letter): Update prototype.
|
|
|
|
|
|
* config/tc-ns32k.c (md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-or1k.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-pdp11.c (struct pdp11_code): Constify error.
|
|
|
|
|
|
(md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-pj.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-ppc.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-rl78.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-rx.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-s390.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-score.c (s3_atof, md_atof): Likewise.
|
|
|
|
|
|
* config/tc-sh.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-sparc.c (struct sparc_it): Constify error.
|
|
|
|
|
|
(md_atof): Return const char*.
|
|
|
|
|
|
* config/tc-spu.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-tic30.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-tic4x.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-tic6x.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-tilegx.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-tilepro.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-v850.c (parse_register_list, md_atof): Likewise.
|
|
|
|
|
|
* config/tc-vax.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-visium.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-xc16x.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-xgate.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-xstormy16.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-z80.c (md_atof): Likewise.
|
|
|
|
|
|
* config/tc-z8k.c (md_atof): Likewise.
|
|
|
|
|
|
|
2016-03-20 13:37:55 +08:00
|
|
|
|
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (struct rename_section_struct): Make old_name
|
|
|
|
|
|
const.
|
|
|
|
|
|
(xtensa_section_rename): Make argument type const char *.
|
|
|
|
|
|
* config/tc-xtensa.h (xtensa_section_rename): Adjust.
|
|
|
|
|
|
|
2016-03-24 19:52:39 +08:00
|
|
|
|
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i960.c (parse_ldconst): Cast to char * when assigning to
|
|
|
|
|
|
args[0].
|
|
|
|
|
|
|
2016-03-20 13:13:05 +08:00
|
|
|
|
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-m32c.c (m32c_md_end): cast the argument to md_assemble to
|
|
|
|
|
|
char *.
|
|
|
|
|
|
(m32c_indirect_operand): Likewise.
|
|
|
|
|
|
* config/tc-nds32.c (do_pseudo_b): Likewise.
|
|
|
|
|
|
(do_pseudo_bal): Likewise.
|
|
|
|
|
|
(do_pseudo_ls_bhw): Likewise.
|
|
|
|
|
|
|
2016-02-23 06:27:30 +08:00
|
|
|
|
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* as.c (parse_args): Cast literal to char * when assigning to optarg.
|
|
|
|
|
|
|
2016-02-29 06:21:12 +08:00
|
|
|
|
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ia64.c (md_assemble): Add temporary variable to pass to
|
|
|
|
|
|
get_symbol_name ().
|
|
|
|
|
|
* config/tc-sparc.c (s_register): Cast a literal to char * in
|
|
|
|
|
|
assignment.
|
|
|
|
|
|
|
2016-02-23 05:17:14 +08:00
|
|
|
|
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i960.c (parse_expr): Cast to char * when assigning to
|
|
|
|
|
|
input_line_pointer.
|
|
|
|
|
|
* config/tc-m32r.c (expand_debug_syms): Likewise.
|
|
|
|
|
|
* config/tc-msp430.c (msp430_dstoperand): Likewise.
|
|
|
|
|
|
* config/tc-z80.c (md_begin): Likewise.
|
|
|
|
|
|
* stabs.c (stabs_generate_asm_func): Likewise.
|
|
|
|
|
|
|
2016-03-27 16:30:31 +08:00
|
|
|
|
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* cgen.c: Modernize the way functions declare arguments.
|
|
|
|
|
|
* config/tc-bfin.c: Likewise.
|
|
|
|
|
|
* config/tc-pdp11.c: Likewise.
|
|
|
|
|
|
* literal.c: Likewise.
|
|
|
|
|
|
* read.c: Likewise.
|
|
|
|
|
|
* stabs.c: Likewise.
|
|
|
|
|
|
|
2016-03-27 19:07:27 +08:00
|
|
|
|
2016-03-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_handle_align): Make the type of some
|
|
|
|
|
|
variables unsigned char[].
|
|
|
|
|
|
* config/tc-alpha.c (alpha_handle_align): Likewise.
|
|
|
|
|
|
* config/tc-arm.c (arm_handle_align): Likewise.
|
|
|
|
|
|
* config/tc-z80.c: Likewise.
|
|
|
|
|
|
|
2016-03-30 23:18:04 +08:00
|
|
|
|
2016-03-30 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/19880
|
|
|
|
|
|
* config/tc-arm.c (do_t_push_pop): Cast bitmask to unsigned before
|
|
|
|
|
|
shifting.
|
|
|
|
|
|
|
2016-03-30 22:21:25 +08:00
|
|
|
|
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* testsuite/gas/all/gas.exp: Don't xfail on ARC.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Likewise.
|
|
|
|
|
|
* testsuite/gas/all/redef3.d: Allow execution for ARC.
|
2016-03-30 22:21:25 +08:00
|
|
|
|
|
2016-03-30 22:09:56 +08:00
|
|
|
|
2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* testsuite/gas/arc/warn.exp: Fix matching pattern.
|
2016-03-30 22:09:56 +08:00
|
|
|
|
|
[ARC] Add support for Quarkse opcodes.
gas/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
opcodes/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (invld07): Remove.
* arc-ext-tbl.h: New file.
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
* arc-opc.c (arc_opcodes): Add ext-tbl include.
include/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 20:49:22 +08:00
|
|
|
|
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* testsuite/gas/arc/ext2op.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/ext2op.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/ext3op.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/ext3op.s: Likewise.
|
[ARC] Add support for Quarkse opcodes.
gas/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
opcodes/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (invld07): Remove.
* arc-ext-tbl.h: New file.
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
* arc-opc.c (arc_opcodes): Add ext-tbl include.
include/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 20:49:22 +08:00
|
|
|
|
|
2016-02-27 22:35:32 +08:00
|
|
|
|
2016-03-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (struct aarch64_long_option_table): Ad const
|
|
|
|
|
|
qualifier.
|
|
|
|
|
|
* config/tc-alpha.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-arc.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-arm.c (struct arm_long_option_table): Likewise.
|
|
|
|
|
|
(md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-avr.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-bfin.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-cr16.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-cris.c (s_cris_arch): Likewise.
|
|
|
|
|
|
(md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-crx.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-d10v.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-d30v.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-dlx.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-epiphany.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-fr30.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-frv.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-ft32.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-h8300.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-hppa.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-i370.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-i386.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-i860.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-i960.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-ia64.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-ip2k.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-iq2000.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-lm32.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-m32c.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-m32r.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-m68hc11.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-m68k.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-mcore.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-mep.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-metag.c (struct metag_long_option): Likewise.
|
|
|
|
|
|
(md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.h (md_parse_option): Remove prototype.
|
|
|
|
|
|
* config/tc-mips.c (md_parse_option): Adjust.
|
|
|
|
|
|
* config/tc-mmix.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-mn10300.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-moxie.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-msp430.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-mt.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-nds32.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-nds32.h (nds32_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-nios2.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-ns32k.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-or1k.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-pdp11.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-pj.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-ppc.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-rl78.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-rx.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-s390.c (s390_parse_cpu): Likewise.
|
|
|
|
|
|
* config/tc-score.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-sh.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-sparc.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-spu.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-tic30.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-tic4x.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-tic6x.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-tilegx.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-tilepro.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-v850.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-vax.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-visium.c (struct visium_long_option_table): Likewise.
|
|
|
|
|
|
* config/tc-xc16x.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-xgate.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-xstormy16.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-z80.c (md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-z8k.c (md_parse_option): Likewise.
|
|
|
|
|
|
* tc.h (md_parse_option): Likewise.
|
|
|
|
|
|
|
2016-03-29 19:40:22 +08:00
|
|
|
|
2016-03-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-bfin.c (gencode): Use XOBNEW obstack_alloc () wrapper.
|
|
|
|
|
|
* config/tc-hppa.c (fix_new_hppa): Likewise.
|
|
|
|
|
|
(pa_vtable_entry): Likewise.
|
|
|
|
|
|
(pa_vtable_inherit): Likewise.
|
|
|
|
|
|
* config/tc-m68k.c (md_begin): Likewise.
|
|
|
|
|
|
|
2016-03-24 10:39:13 +08:00
|
|
|
|
2016-03-28 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_section_name): Return const char *.
|
|
|
|
|
|
* config/obj-elf.h (obj_elf_section_name): Adjust.
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_parse_features): Likewise.
|
|
|
|
|
|
(aarch64_parse_cpu): Likewise.
|
|
|
|
|
|
(aarch64_parse_arch): Likewise.
|
|
|
|
|
|
* config/tc-arm.c (arm_parse_extension): Likewise.
|
|
|
|
|
|
(arm_parse_cpu): Likewise.
|
|
|
|
|
|
(arm_parse_arch): Likewise.
|
|
|
|
|
|
* config/tc-nds32.c: Likewise.
|
|
|
|
|
|
* config/xtensa-relax.c (parse_special_fn): Likewise.
|
|
|
|
|
|
* stabs.c (generate_asm_file): Likewise.
|
|
|
|
|
|
|
2016-03-20 13:21:48 +08:00
|
|
|
|
2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-cr16.c (cr16_assemble): New function.
|
|
|
|
|
|
(md_assemble): Call cr16_assemble.
|
|
|
|
|
|
|
2016-03-26 03:43:13 +08:00
|
|
|
|
2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* as.c (parse_args): Adjust.
|
|
|
|
|
|
* as.h (flag_size_check): Rename to flag_allow_nonconst_size.
|
|
|
|
|
|
* config/obj-elf.c (elf_frob_symbol): Adjust.
|
|
|
|
|
|
|
2016-03-25 01:28:41 +08:00
|
|
|
|
2016-03-24 Jose E. Marchesi <jose.marchesi@oracle.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (sparc_ip): Remove the V9 restriction on ASR
|
|
|
|
|
|
registers to be in the 16..31 range.
|
|
|
|
|
|
|
2016-03-20 09:48:07 +08:00
|
|
|
|
2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-microblaze.c (md_assemble): Cast opc to char * when calling
|
|
|
|
|
|
frag_var ().
|
|
|
|
|
|
|
2016-03-19 19:38:46 +08:00
|
|
|
|
2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-visium.c (md_atof): Localize the string returned on
|
|
|
|
|
|
failure.
|
|
|
|
|
|
|
2016-03-20 13:34:02 +08:00
|
|
|
|
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-h8300.c (h8300_elf_section): Add const qualifiers.
|
|
|
|
|
|
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
|
|
|
|
|
|
* config/tc-m68hc11.c (md_begin): Likewise.
|
|
|
|
|
|
(print_opcode_list): Likewise.
|
|
|
|
|
|
* config/tc-msp430.c (msp430_section): Likewise.
|
|
|
|
|
|
* config/tc-score.c (struct s3_insn_to_dependency): Likewise.
|
|
|
|
|
|
(s3_build_dependency_insn_hsh): Likewise.
|
|
|
|
|
|
* config/tc-score7.c (struct s7_insn_to_dependency): Likewise.
|
|
|
|
|
|
(s7_build_dependency_insn_hsh): Likewise.
|
|
|
|
|
|
* config/tc-tic4x.c: Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
|
|
|
|
|
|
(subsym_get_arg): Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c (struct suffix_reloc_map): Likewise.
|
|
|
|
|
|
(get_directive): Likewise.
|
|
|
|
|
|
(cache_literal_section): Likewise.
|
|
|
|
|
|
* config/xtensa-relax.c: Likewise.
|
|
|
|
|
|
* symbols.c (symbol_create): Likewise.
|
|
|
|
|
|
(local_symbol_make): Likewise.
|
|
|
|
|
|
(symbol_relc_make_expr): Likewise.
|
|
|
|
|
|
|
2016-03-20 13:07:55 +08:00
|
|
|
|
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-pdp11.c (md_assemble): Remove useless if and assignment to
|
|
|
|
|
|
str.
|
|
|
|
|
|
|
2016-03-20 13:36:16 +08:00
|
|
|
|
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-sparc.c (sparc_regname_to_dw2regnum): Replace strchr ()
|
|
|
|
|
|
call with a switch.
|
|
|
|
|
|
|
2016-02-29 07:00:00 +08:00
|
|
|
|
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ia64.c (ia64_do_align): Remove.
|
|
|
|
|
|
(ia64_cons_align): Call do_align () directly.
|
|
|
|
|
|
(dot_proc): Likewise.
|
|
|
|
|
|
(stmt_float_cons): Likewise.
|
|
|
|
|
|
|
2016-02-14 11:00:07 +08:00
|
|
|
|
2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* listing.c (listing_message): Use XNEW style allocation macros.
|
|
|
|
|
|
* read.c (read_a_source_file): Likewise.
|
|
|
|
|
|
(read_symbol_name): Likewise.
|
|
|
|
|
|
(s_mri_common): Likewise.
|
|
|
|
|
|
(assign_symbol): Likewise.
|
|
|
|
|
|
(s_reloc): Likewise.
|
|
|
|
|
|
(emit_expr_with_reloc): Likewise.
|
|
|
|
|
|
(s_incbin): Likewise.
|
|
|
|
|
|
(s_include): Likewise.
|
|
|
|
|
|
* sb.c (sb_build): Likewise.
|
|
|
|
|
|
(sb_check): Likewise.
|
|
|
|
|
|
|
2016-03-22 20:18:37 +08:00
|
|
|
|
2016-03-22 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* write.c (record_alignment): Revert 2016-02-18 change.
|
|
|
|
|
|
|
2016-03-22 20:08:53 +08:00
|
|
|
|
2016-03-22 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-alpha.c (load_expression): Replace alloca with xmalloc.
|
|
|
|
|
|
(emit_jsrjmp, tc_gen_reloc): Likewise.
|
|
|
|
|
|
* config/tc-i370.c (i370_macro): Likewise.
|
|
|
|
|
|
|
2016-03-22 17:41:16 +08:00
|
|
|
|
2016-03-22 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2016-03-16 06:01:34 +08:00
|
|
|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/nps400-0.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-0.s: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-1.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/nps400-1.s: New file.
|
|
|
|
|
|
|
arc/opcodes: Use flag operand class to handle multiple flag matches
When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled. For example:
adc.n.eq r0,r0,r2
Will assemble without error, yet, upon disassembly, the instruction will
actually be:
adc.c r0,r0,r2
In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match. Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.
To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used. Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags. However, at present, the class type is never used. The current
values identify the type of instruction that the flag will be used in,
but this is not required information.
Instead, this commit discards the old flag classes, and introduces 3 new
classes. The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class. The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.
The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction. The
"at most" one means that no flags being present is fine.
The class F_FLAG_REQUIRED is not currently used, but will be soon. With
this class, exactly one of the flags from this class must be present in
the instruction. If the flag class contains a single flag, then of
course that flag must be present. However, if the flag class contained
two or more, then one, and only one of them must be present.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
Handle flag class.
* testsuite/gas/arc/asm-errors.d: New file.
* testsuite/gas/arc/asm-errors.err: New file.
* testsuite/gas/arc/asm-errors.s: New file.
include/ChangeLog:
* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
new classes instead.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_classes): Convert all flag classes to use
the new class enum values.
2016-03-15 06:17:47 +08:00
|
|
|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
|
|
|
|
|
|
declarations to start of block. Reset code on all flags before
|
|
|
|
|
|
attempting to match them. Handle multiple hits on the same flag.
|
|
|
|
|
|
Handle flag class.
|
|
|
|
|
|
* testsuite/gas/arc/asm-errors.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/asm-errors.err: New file.
|
|
|
|
|
|
* testsuite/gas/arc/asm-errors.s: New file.
|
|
|
|
|
|
|
2016-03-16 05:51:50 +08:00
|
|
|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (cpu_types): Add nps400 entry.
|
|
|
|
|
|
(check_zol): Handle nps400.
|
|
|
|
|
|
|
arc: Remove EF_ARC_CPU_GENERIC constant.
The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h
file, and is used in a few places in binutils, however, this constant
should never make it into the elf header flags; we always set a valid
cpu type in the assembler, which should then be copied over during
linking.
There are some non-gnu arc compilers that don't write an architecture
type into the e_flags field, instead leaving the field as 0, which is
the EF_ARC_CPU_GENERIC value. This non-gnu compiler uses the machine
type to distinguish between the old and newer arc architectures, setting
the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700
architectures, while using EM_ARC_COMPACT2 for newer arcem and archs
architectures.
Previously when displaying the machine flags for an older EM_ARC_COMPACT
machine, if the e_flags had not been filled in, then we relied on the
default case statement to display the message "Generic ARCompact", while
in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC
to print "ARC Generic", leaving the default case to print a message
about unrecognised cpu flag.
After this commit EF_ARC_CPU_GENERIC has been removed, for both machine
types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case
statement to handle the situation where the e_flags has not been filled
in. The message displayed is now "Unknown ARCompact" (for older arc
architectures) and "Unknown ARC" (for the newer architectures). The
switch from "Generic" to "Unknown" in the message string is for clarity,
calling the file "Generic" can give the impression that the file is
compiled for a common sub-set of the architectures, and would therefore
run on any type of machine (or at least any type of new or old machine
depending on if the machine type is ARC or ARCv2). However, this was
not what "Generic" meant, it really meant "Unknown", so that's what we
now say.
As part of the merging of the readelf flag reading code, I have unified
the strings used in displaying the ELF ABI. This means that for older
arc machines (arc600, arc601, and arc700) the string used for the
original ABI, and ABIv2 have changed, the current ABIv3 remains the
same. For the newer architectures (arcem and archs) the abi strings
remain unchanged in all cases.
bfd/ChangeLog:
* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
EF_ARC_CPU_GENERIC.
(arc_elf_final_write_processing): Don't bother setting cpu field
in e_flags, this will have been set elsewhere.
binutils/ChangeLog:
* readelf.c (get_machine_flags): Move arc processing into...
(decode_ARC_machine_flags): ... new function. Remove use of
EF_ARC_CPU_GENERIC, change default case from "generic arc" to
"unknown arc". Merged ABI printing between two machine types.
gas/ChangeLog:
* config/tc-arc.c (arc_select_cpu): Remove use of
EF_ARC_CPU_GENERIC.
include/ChangeLog:
* elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
2016-03-16 05:38:30 +08:00
|
|
|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (arc_select_cpu): Remove use of
|
|
|
|
|
|
EF_ARC_CPU_GENERIC.
|
|
|
|
|
|
|
2016-03-01 19:41:12 +08:00
|
|
|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (arc_target): Delay initialisation until
|
|
|
|
|
|
arc_select_cpu.
|
|
|
|
|
|
(arc_target_name): Likewise.
|
|
|
|
|
|
(arc_features): Likewise.
|
|
|
|
|
|
(arc_mach_type): Likewise.
|
|
|
|
|
|
(cpu_types): Remove "all" entry.
|
|
|
|
|
|
(arc_select_cpu): New function, most of the content is from...
|
|
|
|
|
|
(md_parse_option): ... here. Call new arc_select_cpu.
|
|
|
|
|
|
(md_begin): Call arc_select_cpu if needed, default is now arc700.
|
|
|
|
|
|
|
2016-03-16 06:38:41 +08:00
|
|
|
|
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/inline-data-1.d: Add target restriction.
|
|
|
|
|
|
* testsuite/gas/arc/inline-data-2.d: New file.
|
|
|
|
|
|
|
2016-03-22 00:31:46 +08:00
|
|
|
|
2016-03-21 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* atof-generic.c: Replace use of alloca with call to xmalloc.
|
|
|
|
|
|
* cgen.c: Likewise.
|
|
|
|
|
|
* dwarf2dbg.c: Likewise.
|
|
|
|
|
|
* macro.c: Likewise.
|
|
|
|
|
|
* remap.c: Likewise.
|
|
|
|
|
|
* stabs.c: Likewise.
|
|
|
|
|
|
* symbols.c: Likewise.
|
|
|
|
|
|
* config/obj-elf.c: Likewise.
|
|
|
|
|
|
* config/tc-aarch64.c: Likewise.
|
|
|
|
|
|
* config/tc-arc.c: Likewise.
|
|
|
|
|
|
* config/tc-arm.c: Likewise.
|
|
|
|
|
|
* config/tc-avr.c: Likewise.
|
|
|
|
|
|
* config/tc-ia64.c: Likewise.
|
|
|
|
|
|
* config/tc-mips.c: Likewise.
|
|
|
|
|
|
* config/tc-msp430.c: Likewise.
|
|
|
|
|
|
* config/tc-nds32.c: Likewise.
|
|
|
|
|
|
* config/tc-ppc.c: Likewise.
|
|
|
|
|
|
* config/tc-sh.c: Likewise.
|
|
|
|
|
|
* config/tc-tic30.c: Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c: Likewise.
|
|
|
|
|
|
* config/tc-xstormy16.c: Likewise.
|
|
|
|
|
|
* config/te-vms.c: Likewise.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2016-02-15 03:41:38 +08:00
|
|
|
|
2016-03-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* tc-i386.c (f32_1): Change type to unsigned char[].
|
|
|
|
|
|
(f32_2): Likewise.
|
|
|
|
|
|
(f32_3): Likewise.
|
|
|
|
|
|
(f32_4): Likewise.
|
|
|
|
|
|
(f32_5): Likewise.
|
|
|
|
|
|
(f32_6): Likewise.
|
|
|
|
|
|
(f32_7): Likewise.
|
|
|
|
|
|
(f32_8): Likewise.
|
|
|
|
|
|
(f32_9): Likewise.
|
|
|
|
|
|
(f32_10): Likewise.
|
|
|
|
|
|
(f32_11): Likewise.
|
|
|
|
|
|
(f32_12): Likewise.
|
|
|
|
|
|
(f32_13): Likewise.
|
|
|
|
|
|
(f32_14): Likewise.
|
|
|
|
|
|
(f16_3): Likewise.
|
|
|
|
|
|
(f16_4): Likewise.
|
|
|
|
|
|
(f16_5): Likewise.
|
|
|
|
|
|
(f16_6): Likewise.
|
|
|
|
|
|
(f16_7): Likewise.
|
|
|
|
|
|
(f16_8): Likewise.
|
|
|
|
|
|
(jump_31): Likewise.
|
|
|
|
|
|
(f32_patt): Likewise.
|
|
|
|
|
|
(f16_patt): Likewise.
|
|
|
|
|
|
(alt_3): Likewise.
|
|
|
|
|
|
(alt_4): Likewise.
|
|
|
|
|
|
(alt_5): Likewise.
|
|
|
|
|
|
(alt_6): Likewise.
|
|
|
|
|
|
(alt_7): Likewise.
|
|
|
|
|
|
(alt_8): Likewise.
|
|
|
|
|
|
(alt_9): Likewise.
|
|
|
|
|
|
(alt_10): Likewise.
|
|
|
|
|
|
(alt_patt): Likewise.
|
|
|
|
|
|
|
2016-03-18 21:07:33 +08:00
|
|
|
|
2016-03-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
2016-03-19 01:30:12 +08:00
|
|
|
|
* doc/c-aarch64.texi (AArch64 Directives): Add descriptions of
|
|
|
|
|
|
.cpu, .dword, .even, .inst. .tlsdescadd, .tlsdesccall,
|
|
|
|
|
|
.tlsdescldr and .xword directives.
|
|
|
|
|
|
|
2016-03-19 01:02:20 +08:00
|
|
|
|
PR target/19721
|
|
|
|
|
|
* testsuite/gas/aarch64/pr19721.s: New test source file.
|
|
|
|
|
|
* testsuite/gas/aarch64/pr19721.d: New test driver file.
|
|
|
|
|
|
|
2016-03-18 21:07:33 +08:00
|
|
|
|
* doc/as.texinfo: Place the target specific command line options
|
|
|
|
|
|
into their own man page section.
|
|
|
|
|
|
|
2016-03-17 00:11:59 +08:00
|
|
|
|
2016-03-16 Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (N_S_32): New.
|
|
|
|
|
|
(N_F_16_32): Likewise.
|
|
|
|
|
|
(N_SUF_32): Support N_F16.
|
|
|
|
|
|
(N_IF_32): Likewise.
|
|
|
|
|
|
(neon_dyadic_misc): Likewise.
|
|
|
|
|
|
(do_neon_cmp): Likewise.
|
|
|
|
|
|
(do_neon_cmp_inv): Likewise.
|
|
|
|
|
|
(do_neon_mul): Likewise.
|
|
|
|
|
|
(do_neon_fcmp_absolute): Likewise.
|
|
|
|
|
|
(do_neon_step): Likewise.
|
|
|
|
|
|
(do_neon_abs_neg): Likewise.
|
|
|
|
|
|
(CVT_FLAVOR_VAR): Likewise.
|
|
|
|
|
|
(do_neon_cvt_1): Likewise.
|
|
|
|
|
|
(do_neon_recip_est): Likewise.
|
|
|
|
|
|
(do_vmaxnm): Likewise.
|
|
|
|
|
|
(do_vrint_1): Likewise.
|
|
|
|
|
|
(neon_check_type): Check architecture support for FP16 extension.
|
|
|
|
|
|
(insns): Update comments.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd.s: New test source.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for
|
|
|
|
|
|
arm mode.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for
|
|
|
|
|
|
thumb mode.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection
|
|
|
|
|
|
error file.
|
|
|
|
|
|
|
2016-03-16 19:33:55 +08:00
|
|
|
|
2016-03-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* read.c (emit_expr_with_reloc): Add code check a bignum with
|
|
|
|
|
|
nbytes == 1.
|
|
|
|
|
|
* config/rx/rx-parse.y (rx_intop): Accept bignum values for sizes
|
|
|
|
|
|
other than 32-bits.
|
|
|
|
|
|
* testsuite/gas/elf/bignum.s: New test source file.
|
|
|
|
|
|
* testsuite/gas/elf/bignum.d: New test driver file.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run the new test.
|
|
|
|
|
|
|
2016-03-15 19:00:28 +08:00
|
|
|
|
2016-03-15 Ulrich Drepper <drepper@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-i386.texi (Register Naming): Update to details of the
|
2016-04-07 21:43:14 +08:00
|
|
|
|
latest architecture version.
|
2016-03-15 19:00:28 +08:00
|
|
|
|
|
2016-03-11 00:05:29 +08:00
|
|
|
|
2016-03-10 Mickael Guene <mickael.guene@st.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19744
|
|
|
|
|
|
* config/tc-arm.c (do_arit): Protect against bad relocations usage.
|
|
|
|
|
|
(do_mov): Likewise.
|
|
|
|
|
|
(do_t_add_sub): Allow pcrop relocations for Thumb-2 targets.
|
|
|
|
|
|
(do_t_mov_cmp): Likewise.
|
|
|
|
|
|
(do_t_add_sub): Protect against bad relocations usage.
|
|
|
|
|
|
(do_t_mov_cmp): Likewise.
|
2016-03-17 07:27:50 +08:00
|
|
|
|
* testsuite/gas/arm/adds-thumb1-reloc-local-armv7-m.s: New.
|
|
|
|
|
|
* testsuite/gas/arm/adds-thumb1-reloc-local-armv7-m.d: New.
|
|
|
|
|
|
* testsuite/gas/arm/movs-thumb1-reloc-local-armv7-m.s: New.
|
|
|
|
|
|
* testsuite/gas/arm/movs-thumb1-reloc-local-armv7-m.d: New.
|
2016-03-11 00:05:29 +08:00
|
|
|
|
|
2016-03-09 09:02:07 +08:00
|
|
|
|
2016-03-09 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (neon_alignment_bit): Rename do_align to
|
|
|
|
|
|
do_alignment.
|
|
|
|
|
|
(do_neon_ld_st_lane): Likewise.
|
|
|
|
|
|
(do_neon_ld_dup): Likewise.
|
|
|
|
|
|
|
2016-03-08 21:19:52 +08:00
|
|
|
|
2016-03-08 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arc/inline-data-1.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/inline-data-1.s: New file.
|
|
|
|
|
|
|
2016-03-08 01:31:57 +08:00
|
|
|
|
2016-03-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_cpus): Add cortex-r8.
|
|
|
|
|
|
* doc/c-arm.texi: Add cortex-r8.
|
|
|
|
|
|
|
2016-03-07 23:16:28 +08:00
|
|
|
|
2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c: Add const qualifiers.
|
|
|
|
|
|
* config/tc-h8300.c (md_begin): Likewise.
|
|
|
|
|
|
* config/tc-ia64.c (print_prmask): Likewise.
|
|
|
|
|
|
* config/tc-msp430.c (msp430_operands): Likewise.
|
|
|
|
|
|
* config/tc-nds32.c (struct suffix_name): Likewise.
|
|
|
|
|
|
(struct nds32_parse_option_table): Likewise.
|
|
|
|
|
|
(struct nds32_set_option_table): Likewise.
|
|
|
|
|
|
(do_pseudo_pushpopm): Likewise.
|
|
|
|
|
|
(do_pseudo_pushpop_stack): Likewise.
|
|
|
|
|
|
(nds32_relax_relocs): Likewise.
|
|
|
|
|
|
(nds32_flag): Likewise.
|
|
|
|
|
|
(struct nds32_hint_map): Likewise.
|
|
|
|
|
|
(nds32_find_reloc_table): Likewise.
|
|
|
|
|
|
(nds32_match_hint_insn): Likewise.
|
|
|
|
|
|
* config/tc-s390.c: Likewise.
|
|
|
|
|
|
* config/tc-sh.c (get_specific): Likewise.
|
|
|
|
|
|
* config/tc-tic30.c: Likewise.
|
|
|
|
|
|
* config/tc-tic4x.c (tic4x_inst_add): Likewise.
|
|
|
|
|
|
(tic4x_indirect_parse): Likewise.
|
|
|
|
|
|
* config/tc-vax.c (vax_cons): Likewise.
|
|
|
|
|
|
* config/tc-z80.c (struct reg_entry): Likewise.
|
|
|
|
|
|
* config/tc-epiphany.c (md_assemble): Adjust.
|
|
|
|
|
|
(epiphany_assemble): New function.
|
|
|
|
|
|
(epiphany_elf_section_rtn): Call do_align directly.
|
|
|
|
|
|
(epiphany_elf_section_text): Likewise.
|
|
|
|
|
|
* config/tc-ip2k.c (ip2k_elf_section_rtn): Likewise.
|
|
|
|
|
|
(ip2k_elf_section_text): Likewise.
|
|
|
|
|
|
* read.c (do_align): Make it not static.
|
|
|
|
|
|
* read.h (do_align): New prototype.
|
|
|
|
|
|
|
2016-03-04 22:16:48 +08:00
|
|
|
|
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (aeabi_set_public_attributes): Emit attribute
|
|
|
|
|
|
for ARMv8.1 AdvSIMD use.
|
|
|
|
|
|
* testsuite/gas/arm/attr-march-armv8-a+rdma.d: New.
|
|
|
|
|
|
* testsuite/gas/arm/attr-march-armv8_1-a+simd.d: New.
|
|
|
|
|
|
|
2016-03-04 19:28:28 +08:00
|
|
|
|
2016-03-04 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA
|
|
|
|
|
|
feature.
|
|
|
|
|
|
(record_feature_use): New.
|
|
|
|
|
|
(mark_feature_used): Use record_feature_use.
|
|
|
|
|
|
(do_neon_qrdmlah): New.
|
|
|
|
|
|
(insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and
|
|
|
|
|
|
variants.
|
|
|
|
|
|
(arm_extensions): Put into alphabetical order. Re-indent "simd"
|
|
|
|
|
|
and "rdma" entries. Fix the incorrect merge value for "+rdma".
|
|
|
|
|
|
* testsuite/gas/arm/armv8-a+rdma-warning.d: New.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options.
|
|
|
|
|
|
Make source file explicit.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-a+rdma.l: New.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension
|
|
|
|
|
|
directives. Fix white-space.
|
|
|
|
|
|
* testsuite/gas/arm/armv8_1-a+simd.d: New.
|
|
|
|
|
|
|
2016-03-02 21:15:32 +08:00
|
|
|
|
2016-03-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
|
|
|
|
|
|
|
2016-02-29 23:51:11 +08:00
|
|
|
|
2016-02-29 Cupertino Miranda <cmiranda@synopsys.com>
|
|
|
|
|
|
Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* config/tc-arc.c (arc_extra_reloc): Change size to 0.
|
|
|
|
|
|
(tc_arc_fix_adjustable): Changed default return value to 1.
|
|
|
|
|
|
* testsuite/gas/arc/j.d: Updated expected symbol
|
|
|
|
|
|
* testsuite/gas/arc/jl.d: Likewise
|
|
|
|
|
|
* testsuite/gas/arc/relax-avoid1.d: Likewise
|
|
|
|
|
|
* testsuite/gas/arc/st.d: Likewise
|
2016-02-29 23:51:11 +08:00
|
|
|
|
|
2016-02-29 23:07:48 +08:00
|
|
|
|
2016-02-29 Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c: Enable code density instructions for ARC EM.
|
|
|
|
|
|
|
2016-02-26 22:44:03 +08:00
|
|
|
|
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR ld/19645
|
|
|
|
|
|
* NEWS: Mention --enable-elf-stt-common and --elf-stt-common=
|
|
|
|
|
|
for ELF assemblers.
|
|
|
|
|
|
* as.c (flag_use_elf_stt_common): New.
|
|
|
|
|
|
(show_usage): Add --elf-stt-common=.
|
|
|
|
|
|
(option_values): Add OPTION_ELF_STT_COMMON.
|
|
|
|
|
|
(std_longopts): Add --elf-stt-common=.
|
|
|
|
|
|
(parse_args): Handle --elf-stt-common=.
|
|
|
|
|
|
* as.h (flag_use_elf_stt_common): New.
|
|
|
|
|
|
* config.in: Regenerated.
|
|
|
|
|
|
* configure: Likewise.
|
|
|
|
|
|
* configure.ac: Add --enable-elf-stt-common and define
|
|
|
|
|
|
DEFAULT_GENERATE_ELF_STT_COMMON.
|
|
|
|
|
|
* gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON
|
|
|
|
|
|
and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set.
|
|
|
|
|
|
* doc/as.texinfo: Document --elf-stt-common=.
|
|
|
|
|
|
* testsuite/gas/elf/common3.s: New file.
|
|
|
|
|
|
* testsuite/gas/elf/common3a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/common3b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/common4.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/common4a.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/common4b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/dw2-compress-3b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/dw2-compressed-3b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a
|
|
|
|
|
|
and common4b.
|
|
|
|
|
|
* testsuite/gas/i386/dw2-compress-3.d: Renamed to ...
|
|
|
|
|
|
* testsuite/gas/i386/dw2-compress-3a.d: This. Pass
|
|
|
|
|
|
--elf-stt-common=no to as.
|
|
|
|
|
|
* testsuite/gas/i386/dw2-compressed-3.d: Renamed to ...
|
|
|
|
|
|
* testsuite/gas/i386/dw2-compressed-3a.d: This. Pass
|
|
|
|
|
|
--elf-stt-common=no to as.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run dw2-compress-3a,
|
|
|
|
|
|
dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead
|
|
|
|
|
|
of dw2-compress-3 and dw2-compressed-3.
|
|
|
|
|
|
|
2016-02-26 00:55:21 +08:00
|
|
|
|
2016-02-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* as.c (select_emulation_mode): Add const qualifiers.
|
|
|
|
|
|
* as.h: Likewise.
|
|
|
|
|
|
* config/bfin-defs.h: Likewise.
|
|
|
|
|
|
* config/bfin-parse.y: Likewise.
|
|
|
|
|
|
* config/rx-parse.y: Likewise.
|
|
|
|
|
|
* config/tc-aarch64.c (struct aarch64_option_table): Likewise.
|
|
|
|
|
|
(struct aarch64_cpu_option_table): Likewise.
|
|
|
|
|
|
(struct aarch64_arch_option_table): Likewise.
|
|
|
|
|
|
(struct aarch64_option_cpu_value_table): Likewise.
|
|
|
|
|
|
(struct aarch64_long_option_table): Likewise.
|
|
|
|
|
|
(struct aarch64_option_abi_value_table): Likewise.
|
|
|
|
|
|
* config/tc-arm.c (struct reloc_entry): Likewise.
|
|
|
|
|
|
(tc_gen_reloc): Likewise.
|
|
|
|
|
|
(struct arm_option_table): Likewise.
|
|
|
|
|
|
(struct arm_legacy_option_table): Likewise.
|
|
|
|
|
|
(struct arm_cpu_option_table): Likewise.
|
|
|
|
|
|
(struct arm_arch_option_table): Likewise.
|
|
|
|
|
|
(struct arm_option_extension_value_table): Likewise.
|
|
|
|
|
|
(struct arm_option_fpu_value_table): Likewise.
|
|
|
|
|
|
(struct arm_option_value_table): Likewise.
|
|
|
|
|
|
(struct arm_long_option_table): Likewise.
|
|
|
|
|
|
* config/tc-avr.c (struct avr_opcodes_s): Likewise.
|
|
|
|
|
|
(struct mcu_type_s): Likewise.
|
|
|
|
|
|
(struct exp_mod_s): Likewise.
|
|
|
|
|
|
(avr_operand): Likewise.
|
|
|
|
|
|
(avr_operands): Likewise.
|
|
|
|
|
|
* config/tc-d10v.c (md_begin): Likewise.
|
|
|
|
|
|
* config/tc-dlx.c: Likewise.
|
|
|
|
|
|
* config/tc-fr30.c (fr30_is_colon_insn): Likewise.
|
|
|
|
|
|
* config/tc-ft32.c (parse_condition): Likewise.
|
|
|
|
|
|
* config/tc-h8300.c (do_a_fix_imm): Likewise.
|
|
|
|
|
|
* config/tc-hppa.c (pa_ip): Likewise.
|
|
|
|
|
|
(hppa_regname_to_dw2regnum): Likewise.
|
|
|
|
|
|
* config/tc-i370.c (i370_elf_suffix): Likewise.
|
|
|
|
|
|
* config/tc-i960.c (struct tabentry): Likewise.
|
|
|
|
|
|
* config/tc-m32r.c: Likewise.
|
|
|
|
|
|
* config/tc-m68k.c: Likewise.
|
|
|
|
|
|
* config/tc-m68k.h: Likewise.
|
|
|
|
|
|
* config/tc-mcore.c (parse_psrmod): Likewise.
|
|
|
|
|
|
* config/tc-metag.c (struct metag_core_option): Likewise.
|
|
|
|
|
|
(struct metag_long_option): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.c: Likewise.
|
|
|
|
|
|
* config/tc-mips.c (macro): Likewise.
|
|
|
|
|
|
* config/tc-mn10200.c: Likewise.
|
|
|
|
|
|
* config/tc-mn10300.c: Likewise.
|
|
|
|
|
|
* config/tc-msp430.c (struct rcodes_s): Likewise.
|
|
|
|
|
|
(struct hcodes_s): Likewise.
|
|
|
|
|
|
(md_parse_option): Likewise.
|
|
|
|
|
|
* config/tc-ns32k.c (struct ns32k_option): Likewise.
|
|
|
|
|
|
(optlist): Likewise.
|
|
|
|
|
|
* config/tc-ppc.c (ppc_elf_suffix): Likewise.
|
|
|
|
|
|
(tc_ppc_regname_to_dw2regnum): Likewise.
|
|
|
|
|
|
* config/tc-ppc.h: Likewise.
|
|
|
|
|
|
* config/tc-rl78.c: Likewise.
|
|
|
|
|
|
* config/tc-rx.c (struct cpu_type): Likewise.
|
|
|
|
|
|
* config/tc-sh.c (sh_regname_to_dw2regnum): Likewise.
|
|
|
|
|
|
* config/tc-sparc.c (struct priv_reg_entry): Likewise.
|
|
|
|
|
|
(sparc_ip): Likewise.
|
|
|
|
|
|
* config/tc-spu.c (insn_fmt_string): Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
|
|
|
|
|
|
* config/tc-v850.c: Likewise.
|
|
|
|
|
|
* config/tc-visium.c (struct visium_arch_option_table): Likewise.
|
|
|
|
|
|
(struct visium_long_option_table): Likewise.
|
|
|
|
|
|
* config/tc-xgate.c: Likewise.
|
|
|
|
|
|
* config/tc-z8k.c: Likewise.
|
|
|
|
|
|
* read.c (add_include_dir): Likewise.
|
|
|
|
|
|
* read.h: Likewise.
|
|
|
|
|
|
|
2016-02-23 08:05:27 +08:00
|
|
|
|
2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/all/gas.exp: Change target pattern to cover
|
|
|
|
|
|
arceb-*.
|
|
|
|
|
|
* testsuite/gas/all/redef3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Likewise.
|
|
|
|
|
|
|
2016-02-25 01:59:35 +08:00
|
|
|
|
2016-02-24 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (BAD_FP16): New error message macro.
|
|
|
|
|
|
(do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2
|
|
|
|
|
|
fp16 scalar instructions.
|
|
|
|
|
|
(neon_check_type): Allow different size from key.
|
|
|
|
|
|
(do_vfp_nsyn_add_sub): Add support SE_H shape support.
|
|
|
|
|
|
(try_vfp_nsyn): Likewise.
|
|
|
|
|
|
(do_vfp_nsyn_mla_mls): Likewise.
|
|
|
|
|
|
(do_vfp_nsyn_fma_fms): Likewise.
|
|
|
|
|
|
(do_vfp_nsyn_ldm_stm): Likewise
|
|
|
|
|
|
(do_vfp_nsyn_sqrt): Likewise
|
|
|
|
|
|
(do_vfp_nsyn_div): Likewise
|
|
|
|
|
|
(do_vfp_nsyn_nmul): Likewise.
|
|
|
|
|
|
(do_vfp_nsyn_cmp): Likewise.
|
|
|
|
|
|
(do_neon_shll): Likewise.
|
|
|
|
|
|
(do_vfp_nsyn_cvt_fpv8): Likewise.
|
|
|
|
|
|
(do_neon_cvttb_2): Likewise.
|
|
|
|
|
|
(do_neon_mov): Likewise.
|
|
|
|
|
|
(do_neon_rshift_round_imm): Likewise.
|
|
|
|
|
|
(do_neon_ldr_str): Likewise.
|
|
|
|
|
|
(do_vfp_nsyn_fpv8): Likewise.
|
|
|
|
|
|
(do_vmaxnm): Likewise.
|
|
|
|
|
|
(do_vrint_1): Likewise.
|
|
|
|
|
|
(insns): New entry for vins, vmovx.
|
|
|
|
|
|
(md_apply_fix): Left shift 1 bit for fp16 vldr/vstr.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-scalar.d: New.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-scalar.s: New.
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New
|
|
|
|
|
|
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New
|
|
|
|
|
|
|
2016-02-24 22:18:16 +08:00
|
|
|
|
2016-02-24 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (NEON_ENC_TAB): Add fp16 instruction shape.
|
|
|
|
|
|
(neon_shape_class): New SC_HALF.
|
|
|
|
|
|
(neon_shape_el): New SE_H.
|
|
|
|
|
|
(neon_shape_el_size): New size for SE_H.
|
|
|
|
|
|
(N_F_ALL): New macro to aggregate N_F16, N_F32, N_64.
|
|
|
|
|
|
(neon_select_shape): Add SE_H support code.
|
|
|
|
|
|
(el_type_of_type_chk): Use N_F_ALL.
|
|
|
|
|
|
(do_vfp_nsyn_cvt): Add SE_H shape support.
|
|
|
|
|
|
(do_neon_cvtz): Likewise.
|
|
|
|
|
|
(do_neon_cvt_1): Likewise.
|
|
|
|
|
|
(do_neon_cvttb_1): Likewise.
|
|
|
|
|
|
|
2016-02-24 22:08:39 +08:00
|
|
|
|
2016-02-24 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/copro.d: Adjust output.
|
|
|
|
|
|
* testsuite/gas/arm/copro.s: Adjust co-processor num.
|
|
|
|
|
|
|
2016-02-24 21:55:30 +08:00
|
|
|
|
2016-02-24 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/mask_1.d: New.
|
|
|
|
|
|
* testsuite/gas/arm/mask_1.s: New.
|
|
|
|
|
|
|
2016-02-24 21:48:59 +08:00
|
|
|
|
2016-02-24 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
|
|
|
|
|
|
* testsuite/gas/arm/copro.d: Update.
|
|
|
|
|
|
|
2016-02-24 18:55:09 +08:00
|
|
|
|
2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_cpus): Add entry for cortex-a32.
|
|
|
|
|
|
* doc/c-arm.texi (ARM Options): Document cortex-a32.
|
|
|
|
|
|
|
2016-02-24 18:53:55 +08:00
|
|
|
|
2016-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* doc/c-arm.texi (ARM Options): Document cortex-a17.
|
2016-02-24 18:53:55 +08:00
|
|
|
|
|
2016-02-24 02:40:03 +08:00
|
|
|
|
2016-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Skip tests for common directive on
|
|
|
|
|
|
hpux.
|
|
|
|
|
|
|
2016-02-22 22:11:27 +08:00
|
|
|
|
2016-02-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* output-file.c (output_file_create): Make file name argument const.
|
|
|
|
|
|
(output_file_close): Likewise.
|
|
|
|
|
|
* output-file.h (output_file_create): Adjust.
|
|
|
|
|
|
(output_file_close): Likewise.
|
|
|
|
|
|
* depend.c (quote_string_for_make): Make src argument const char *.
|
|
|
|
|
|
(register_dependency): Likewise.
|
|
|
|
|
|
(wrap_output): Likewise.
|
|
|
|
|
|
* as.h (register_dependency): Adjust.
|
|
|
|
|
|
* config/tc-xtensa.c (finish_vinsn): Remove unnecessary calls to
|
|
|
|
|
|
as_where ();
|
|
|
|
|
|
* symbols.c (S_SET_EXTERNAL): Likewise.
|
|
|
|
|
|
* input-scrub.c (as_where): Return the file name.
|
|
|
|
|
|
* as.h (as_where): Adjust prototype.
|
|
|
|
|
|
* app.c (do_scrub_chars): Adjust.
|
|
|
|
|
|
* cond.c (s_elseif): Likewise.
|
|
|
|
|
|
(s_else): Likewise.
|
|
|
|
|
|
(initialize_cframe): Likewise.
|
|
|
|
|
|
* config/obj-coff.c (obj_coff_init_stab_section): Likewise.
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_init_stab_section): Likewise.
|
|
|
|
|
|
* config/obj-som.c (obj_som_init_stab_section): Likewise.
|
|
|
|
|
|
* config/tc-aarch64.c (output_info): Likewise.
|
|
|
|
|
|
* config/tc-ia64.c (md_assemble): Likewise.
|
|
|
|
|
|
(dot_alias): Likewise.
|
|
|
|
|
|
* config/tc-m68k.c (m68k_frob_label): Likewise.
|
|
|
|
|
|
* config/tc-mmix.c (s_bspec): Likewise.
|
|
|
|
|
|
(mmix_handle_mmixal): Likewise.
|
|
|
|
|
|
* config/tc-rx.c (rx_include): Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
|
|
|
|
|
|
(tic54x_adjust_symtab): Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c (directive_push): Likewise.
|
|
|
|
|
|
(xtensa_sanity_check): Likewise.
|
|
|
|
|
|
(xtensa_relax_frag): Likewise.
|
|
|
|
|
|
(md_convert_frag): Likewise.
|
|
|
|
|
|
(tinsn_to_slotbuf): Likewise.
|
|
|
|
|
|
* dwarf2dbg.c (dwarf2_where): Likewise.
|
|
|
|
|
|
* ecoff.c (add_file): Likewise.
|
|
|
|
|
|
(ecoff_generate_asm_lineno): Likewise.
|
|
|
|
|
|
* expr.c (make_expr_symbol): Likewise.
|
|
|
|
|
|
* frags.c (frag_new): Likewise.
|
|
|
|
|
|
(frag_var_init): Likewise.
|
|
|
|
|
|
* listing.c (listing_newline): Likewise.
|
|
|
|
|
|
* messages.c (identify): Likewise.
|
|
|
|
|
|
(as_show_where): Likewise.
|
|
|
|
|
|
(as_warn_internal): Likewise.
|
|
|
|
|
|
(as_bad_internal): Likewise.
|
|
|
|
|
|
* read.c (s_irp): Likewise.
|
|
|
|
|
|
(s_macro): Likewise.
|
|
|
|
|
|
(s_reloc): Likewise.
|
|
|
|
|
|
* stabs.c (stabs_generate_asm_file): Likewise.
|
|
|
|
|
|
(stabs_generate_asm_lineno): Likewise.
|
|
|
|
|
|
(stabs_generate_asm_func): Likewise.
|
|
|
|
|
|
* write.c (fix_new_internal): Likewise.
|
|
|
|
|
|
* as.h (PRINTF_WHERE_LIKE): Make file name argument const.
|
|
|
|
|
|
(as_warn_value_out_of_range): Adjust prototype.
|
|
|
|
|
|
(as_bad_value_out_of_range): Adjust prototype.
|
|
|
|
|
|
* messages.c (identify): Make file name argument const char *.
|
|
|
|
|
|
(as_warn_internal): Likewise.
|
|
|
|
|
|
(as_warn_where): Likewise.
|
|
|
|
|
|
(as_bad_internal): Likewise.
|
|
|
|
|
|
(as_bad_where): Likewise.
|
|
|
|
|
|
(as_internal_value_out_of_range): Likewise.
|
|
|
|
|
|
(as_warn_value_out_of_range): Likewise.
|
|
|
|
|
|
(as_bad_value_out_of_range): Likewise.
|
|
|
|
|
|
* as.h (found_comment_file): Change type to const char *.
|
|
|
|
|
|
* cond.c (file_line::file): Likewise.
|
|
|
|
|
|
* config/obj-coff.c (obj_coff_init_stab_section): Make variable const.
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_init_stab_section): Likewise.
|
|
|
|
|
|
* config/obj-som.c (obj_som_init_stab_section): Likewise.
|
|
|
|
|
|
* config/tc-aarch64.c (output_info): Likewise.
|
|
|
|
|
|
* config/tc-alpha.c (insert_operand): Likewise.
|
|
|
|
|
|
* config/tc-arc.c (insert_operand): Likewise.
|
|
|
|
|
|
* config/tc-d30v.c (check_size): Likewise.
|
|
|
|
|
|
* config/tc-ia64.c (struct alias): Likewise.
|
|
|
|
|
|
* config/tc-m68k.c (struct label_line): Likewise.
|
|
|
|
|
|
* config/tc-mcore.c (md_apply_fix): Likewise.
|
|
|
|
|
|
* config/tc-microblaze.c (md_estimate_size_before_relax): Likewise.
|
|
|
|
|
|
* config/tc-mips.c (mips16_immed): Likewise.
|
|
|
|
|
|
* config/tc-mmix.c (mmix_handle_mmixal): Likewise.
|
|
|
|
|
|
* config/tc-ppc.c (ppc_insert_operand): Likewise.
|
|
|
|
|
|
* config/tc-rx.c (rx_include): Likewise.
|
|
|
|
|
|
* config/tc-s390.c (s390_insert_operand): Likewise.
|
|
|
|
|
|
* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
|
|
|
|
|
|
(tic54x_adjust_symtab): Likewise.
|
|
|
|
|
|
* config/tc-tilegx.c (insert_operand): Likewise.
|
|
|
|
|
|
(apply_special_operator): Likewise.
|
|
|
|
|
|
* config/tc-tilepro.c (insert_operand): Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c (directive_push): Likewise.
|
|
|
|
|
|
* ecoff.c (add_file): Likewise.
|
|
|
|
|
|
(ecoff_generate_asm_lineno): Likewise.
|
|
|
|
|
|
* listing.c (listing_newline): Likewise.
|
|
|
|
|
|
* read.c (s_irp): Likewise.
|
|
|
|
|
|
* write.c (install_reloc): Likewise.
|
|
|
|
|
|
* write.h (struct fix): Likewise.
|
|
|
|
|
|
* input-file.c (file_name): Change type to const char *.
|
|
|
|
|
|
(saved_file::file_name): Likewise.
|
|
|
|
|
|
(input_file_open): Change type of argument to const char *.
|
|
|
|
|
|
* input-file.h (input_file_open): Adjust.
|
|
|
|
|
|
* input-scrub.c (logical_input_file): change type to const char *.
|
|
|
|
|
|
(physical_input_file): Likewise.
|
2016-04-07 21:43:14 +08:00
|
|
|
|
(struct input_save): Adjust.
|
2016-02-22 22:11:27 +08:00
|
|
|
|
(input_scrub_push): Adjust.
|
|
|
|
|
|
(input_scrub_begin): Adjust.
|
|
|
|
|
|
(as_where): Adjust.
|
|
|
|
|
|
* input-scrub.c (input_scrub_new_file): Make file name argument const.
|
|
|
|
|
|
(input_scrub_include_file): Likewise.
|
|
|
|
|
|
(new_logical_line_flags): Likewise.
|
|
|
|
|
|
(new_logical_line): Likewise.
|
|
|
|
|
|
* as.h: Adjust.
|
|
|
|
|
|
* frags.h (struct frag): Change type of fr_file to const char *.
|
|
|
|
|
|
* expr.c (expr_symbol_where): Change type of file argument to
|
|
|
|
|
|
const char **.
|
|
|
|
|
|
* expr.h (expr_symbol_where): Likewise.
|
|
|
|
|
|
* config/tc-i370.c (md_apply_fix): adjust.
|
|
|
|
|
|
* config/tc-mmix.c (mmix_md_end): Likewise.
|
|
|
|
|
|
* config/tc-ppc.c (md_apply_fix): Likewise.
|
|
|
|
|
|
* config/tc-s390.c (md_apply_fix): Likewise.
|
|
|
|
|
|
* symbols.c (report_op_error): Likewise.
|
|
|
|
|
|
(resolve_symbol_value): Likewise.
|
|
|
|
|
|
* config/tc-ia64.c (slot::src_file): Change type to const char *.
|
|
|
|
|
|
(rsrc::file): Likewise.
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_sanity_check): Change type of variable to
|
|
|
|
|
|
const char *.
|
|
|
|
|
|
(xtensa_relax_frag): Likewise.
|
|
|
|
|
|
(md_convert_frag): Likewise.
|
|
|
|
|
|
(tinsn_to_slotbuf): Likewise.
|
|
|
|
|
|
* expr.c (expr_symbol_line): Likewise.
|
|
|
|
|
|
* macro.c (define_macro): Likewise.
|
|
|
|
|
|
* macro.h (macro_struct): Likewise.
|
|
|
|
|
|
* messages.c (as_show_where): Likewise.
|
|
|
|
|
|
* read.c (s_macro): Likewise.
|
|
|
|
|
|
* stabs.c (stabs_generate_asm_file): Likewise.
|
|
|
|
|
|
(generate_asm_file): Likewise.
|
|
|
|
|
|
(stabs_generate_asm_lineno): Likewise.
|
|
|
|
|
|
* write.h (struct reloc_list): Likewise.
|
|
|
|
|
|
* input-scrub.c (as_where): Change return type to const char *.
|
|
|
|
|
|
* as.h (as_wheree): Adjust.
|
|
|
|
|
|
|
2016-02-21 22:43:20 +08:00
|
|
|
|
2016-02-21 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* write.c (compress_debug): Move BFD compression bits setting
|
|
|
|
|
|
to ...
|
|
|
|
|
|
(write_object_file): Here.
|
|
|
|
|
|
|
2016-02-21 01:23:20 +08:00
|
|
|
|
2016-02-20 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (register_number): Check RegVRex.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512f.s: Add a test for vgatherqpd
|
|
|
|
|
|
with %zmm19 and %zmm3.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512f-intel.d: Updated.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-avx512f.d: Likewise.
|
|
|
|
|
|
|
2016-02-19 22:27:23 +08:00
|
|
|
|
2016-02-19 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_ext_fp16): New.
|
|
|
|
|
|
(arm_extensions): New entry for "fp16".
|
|
|
|
|
|
|
2016-02-19 21:19:57 +08:00
|
|
|
|
2016-02-19 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 19630
|
|
|
|
|
|
* read.c (read_a_source_file): Check for assemble_one returning
|
|
|
|
|
|
with input_line_pointer set to NULL.
|
|
|
|
|
|
|
2016-02-22 22:11:27 +08:00
|
|
|
|
2016-02-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
|
2016-02-19 20:03:08 +08:00
|
|
|
|
|
2016-02-19 20:13:08 +08:00
|
|
|
|
* listing.c (rebuffer_line): Change return type to void.
|
|
|
|
|
|
|
2016-02-19 20:03:08 +08:00
|
|
|
|
* symbols.c (decode_local_label_name): Make type a const char *.
|
|
|
|
|
|
* listing.c (print_source): Make type of p const char *.
|
|
|
|
|
|
(print_line): Make type of string const char *.
|
|
|
|
|
|
(buffer_line): Return const char *.
|
|
|
|
|
|
(title): Make type const char *.
|
|
|
|
|
|
(subtitle): Likewise.
|
|
|
|
|
|
(listing_listing): Make type of p const char *.
|
|
|
|
|
|
* messages.c (as_internal_value_out_of_range): Make type of prefix
|
|
|
|
|
|
const char *.
|
|
|
|
|
|
* stabs.c (s_stab_generic): make type of stab_secname, stabstr_secname
|
|
|
|
|
|
and string const char *.
|
|
|
|
|
|
* read.c (_bfd_rel): Make type of name const char *.
|
|
|
|
|
|
* app.c (out_string): Change type to const char *.
|
2016-04-07 21:43:14 +08:00
|
|
|
|
(struct app_save::out_string): Likewise.
|
2016-02-19 20:03:08 +08:00
|
|
|
|
|
2016-02-18 17:47:31 +08:00
|
|
|
|
2016-02-18 Dan Gisselquist <dgisselq@verizon.net>
|
|
|
|
|
|
Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* read.c (finish_bundle): Avoid recording a negative alignment.
|
|
|
|
|
|
(do_align): Use unsigned values for n, len and max. Only create
|
|
|
|
|
|
a frag if the alignment requirement is greater than the minimum
|
|
|
|
|
|
byte alignment. Avoid recording a negative alignment.
|
|
|
|
|
|
(s_align): Use unsigned values where appropriate.
|
|
|
|
|
|
(bss_alloc): Use an unsigned value for the alignment.
|
|
|
|
|
|
(sizeof_sleb128): Add a comment noting that we encode one octet
|
|
|
|
|
|
per byte, regardless of the value of OCTETS_PER_BYTE_POWER.
|
|
|
|
|
|
(emit_leb129_expr): Abort if the emitted encoding was longer than
|
|
|
|
|
|
expected.
|
|
|
|
|
|
* read.h (output_leb128): Update prototype.
|
|
|
|
|
|
(sizeof_leb128): Update prototype.
|
|
|
|
|
|
(bss_alloc): Update prototype.
|
|
|
|
|
|
* write.c (record_alignment): Use an unsigned value for the
|
|
|
|
|
|
alignment. Do not record alignments less than the minimum
|
|
|
|
|
|
alignment for a byte.
|
|
|
|
|
|
* write.h (record_alignment): Update prototype.
|
|
|
|
|
|
|
2016-02-16 07:23:28 +08:00
|
|
|
|
2016-02-17 Max Filippov <jcmvbkbc@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (xtensa_move_literals): Fix check for
|
|
|
|
|
|
.init.literal/.fini.literal section name.
|
|
|
|
|
|
* testsuite/gas/xtensa/all.exp: Add init-fini-literals to the
|
|
|
|
|
|
list of xtensa tests.
|
|
|
|
|
|
* testsuite/gas/xtensa/init-fini-literals.d: New file:
|
|
|
|
|
|
init-fini-literals test result patterns.
|
|
|
|
|
|
* testsuite/gas/xtensa/init-fini-literals.s: New file:
|
|
|
|
|
|
init-fini-literals test.
|
|
|
|
|
|
|
2016-02-17 17:55:32 +08:00
|
|
|
|
2016-02-17 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-msp430.c (msp430_mcu_data): Sync with data from TI's
|
|
|
|
|
|
devices.csv file as of March 2016.
|
|
|
|
|
|
|
2016-02-16 22:56:04 +08:00
|
|
|
|
2016-02-16 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.c (tc_arc_frame_initial_instructions): New
|
|
|
|
|
|
function.
|
|
|
|
|
|
(tc_arc_regname_to_dw2regnum): Likewise.
|
|
|
|
|
|
* config/tc-arc.h (TARGET_USE_CFIPOP): Define
|
|
|
|
|
|
(tc_cfi_frame_initial_instructions): Likewise.
|
|
|
|
|
|
(tc_regname_to_dw2regnum): Likewise.
|
2016-03-17 07:27:50 +08:00
|
|
|
|
* testsuite/gas/cfi/cfi-arc-1.d: New file.
|
|
|
|
|
|
* testsuite/gas/cfi/cfi-arc-1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/cfi/cfi.exp: Allow running tests for arc.
|
2016-02-16 22:56:04 +08:00
|
|
|
|
|
2016-02-16 18:37:32 +08:00
|
|
|
|
2016-02-16 Trevor Saunders <tbsaunde@tbsaunde.org>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/internals.texi (S_IS_EXTERN): Remove.
|
|
|
|
|
|
|
2016-02-16 18:35:54 +08:00
|
|
|
|
2016-02-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (Section): Fix up texinfo snafus in previous
|
|
|
|
|
|
update.
|
|
|
|
|
|
|
2016-02-16 18:00:29 +08:00
|
|
|
|
2016-02-16 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19620
|
|
|
|
|
|
* config/tc-aarch64.c (parse_half): Remove restrictions on symbol name.
|
|
|
|
|
|
* testsuite/gas/aarch64/movw_label.d: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/movw_label.s: New.
|
|
|
|
|
|
|
2016-02-16 08:11:23 +08:00
|
|
|
|
2016-02-15 Vinay Kumar G. <Vinay.G@kpit.com>
|
2016-02-16 00:34:34 +08:00
|
|
|
|
|
2016-02-16 00:54:49 +08:00
|
|
|
|
PR gas/19556
|
2016-02-16 00:34:34 +08:00
|
|
|
|
* config/rx-parse.y (MOV): Opcode generation for index
|
|
|
|
|
|
register addressing mode.
|
|
|
|
|
|
* testsuite/gas/rx/rx.exp: Updated for new testcase.
|
|
|
|
|
|
* testsuite/gas/rx/pr19665.s: New file.
|
|
|
|
|
|
* testsuite/gas/rx/pr19665.s: New file.
|
|
|
|
|
|
* testsuite/gas/rx/mov.d: Update expected output.
|
|
|
|
|
|
|
2016-02-16 08:11:23 +08:00
|
|
|
|
2016-02-15 Nick Clifton <nickc@redhat.com>
|
2016-02-15 19:11:46 +08:00
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (.section): Document that numeric values can now
|
|
|
|
|
|
be used for the flags and type fields of the ELF target's .section
|
|
|
|
|
|
directive. Add notes about the restrictions on setting flags and
|
|
|
|
|
|
types.
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_change_section): Allow known sections
|
|
|
|
|
|
to be given processor specific section types. Allow processor and
|
|
|
|
|
|
application specific flags of a section to be set after
|
|
|
|
|
|
definition.
|
|
|
|
|
|
(obj_elf_parse_section_letters): Handle parsing numeric values.
|
|
|
|
|
|
(obj_elf_section_type): Handle parsing numeric values.
|
|
|
|
|
|
(obj_elf_section): Allow numeric type values.
|
|
|
|
|
|
* config/obj-elf.h (obj_elf_change_section): Update prototype.
|
|
|
|
|
|
* testsuite/gas/elf/section10.d: New test.
|
|
|
|
|
|
* testsuite/gas/elf/section10.s: Source file for new test.
|
|
|
|
|
|
* testsuite/gas/elf/elf.exp: Run the new test.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Remove dependency upon
|
|
|
|
|
|
the description of the flags produced by readelf.
|
|
|
|
|
|
* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
|
|
|
|
|
|
* NEWS: Mention the new feature.
|
|
|
|
|
|
|
2016-02-11 23:30:55 +08:00
|
|
|
|
2016-02-11 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19614
|
|
|
|
|
|
* dw2gencfi.c (cfi_sections_set): Delay setting this variable
|
|
|
|
|
|
until it is actually used.
|
|
|
|
|
|
(cfi_set_sections): Set cfi_sections_set to true.
|
|
|
|
|
|
(dot_cfi_startproc): Likewise.
|
|
|
|
|
|
(dot_cfi_endproc): Likewise.
|
|
|
|
|
|
(dot_cfi_fde_data): Likewise.
|
|
|
|
|
|
(cfi_finish): Likewise.
|
|
|
|
|
|
(dot_cfi_sections): Do not set cfi_sections_set.
|
|
|
|
|
|
* doc/as.texinfo (.cfi_sections): Note that targets can provide
|
|
|
|
|
|
their own cfi section name. Also note that the directive can be
|
|
|
|
|
|
reissued provided that CFI generation has not started.
|
|
|
|
|
|
* testsuite/gas/mips/compact-eh-err2.s: Add .cfi_startproc and
|
|
|
|
|
|
.cfi_endproc directives so that the redefinition of .cfi_sections
|
|
|
|
|
|
will trigger the generation of the error message.
|
|
|
|
|
|
* testsuite/gas/mips/compact-eh-err2.l: Update expected line
|
|
|
|
|
|
number of error message.
|
|
|
|
|
|
|
Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
gas/testsuite
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* gas/arc/relax-avoid1.d: New file.
* gas/arc/relax-avoid1.s: Likewise.
* gas/arc/relax-avoid2.d: Likewise.
* gas/arc/relax-avoid2.s: Likewise.
* gas/arc/relax-avoid3.d: Likewise.
* gas/arc/relax-avoid3.s: Likewise.
* gas/arc/relax-b.d: Likewise.
* gas/arc/relax-b.s: Likewise.
include/opcode/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
Declare.
opcodes/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
variable.
2016-02-10 20:09:01 +08:00
|
|
|
|
2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
Janek van Oirschot <jvanoirs@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
|
|
|
|
|
|
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
|
|
|
|
|
|
Define.
|
|
|
|
|
|
(arc_flags, arc_relax_type): New structure.
|
|
|
|
|
|
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
|
|
|
|
|
|
(RELAX_TABLE_ENTRY_MAX): New define.
|
|
|
|
|
|
(relaxation_state, md_relax_table, arc_relaxable_insns)
|
|
|
|
|
|
(arc_num_relaxable_ins): New variable.
|
|
|
|
|
|
(rlx_operand_type, arc_rlx_types): New enums.
|
|
|
|
|
|
(arc_relaxable_ins): New structure.
|
|
|
|
|
|
(OPTION_RELAX): New option.
|
|
|
|
|
|
(arc_insn): New relax member.
|
|
|
|
|
|
(arc_flags): Remove.
|
|
|
|
|
|
(relax_insn_p): New function.
|
|
|
|
|
|
(apply_fixups): Likewise.
|
|
|
|
|
|
(relaxable_operand): Likewise.
|
|
|
|
|
|
(may_relax_expr): Likewise.
|
|
|
|
|
|
(relaxable_flag): Likewise.
|
|
|
|
|
|
(arc_pcrel_adjust): Likewise.
|
|
|
|
|
|
(md_estimate_size_before_relax): Implement.
|
|
|
|
|
|
(md_convert_frag): Likewise.
|
|
|
|
|
|
(md_parse_option): Handle new mrelax option.
|
|
|
|
|
|
(md_show_usage): Likewise.
|
|
|
|
|
|
(assemble_insn): Set relax member.
|
|
|
|
|
|
(emit_insn0): New function.
|
|
|
|
|
|
(emit_insn1): Likewise.
|
|
|
|
|
|
(emit_insn): Handle relaxation case.
|
|
|
|
|
|
* NEWS: Mention the new relaxation option.
|
|
|
|
|
|
* doc/c-arc.texi (ARC Options): Document new mrelax option.
|
|
|
|
|
|
* doc/as.texinfo (Target ARC Options): Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-avoid1.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/relax-avoid1.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-avoid2.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-avoid2.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-avoid3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-avoid3.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-b.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arc/relax-b.s: Likewise.
|
|
|
|
|
|
|
2016-02-08 22:51:10 +08:00
|
|
|
|
2016-02-08 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ia64.c (dot_prologue): Fix formatting.
|
|
|
|
|
|
|
2016-02-04 19:57:57 +08:00
|
|
|
|
2016-02-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_change_section): Remove support for
|
|
|
|
|
|
ARM NOREAD sections.
|
|
|
|
|
|
* config/tc-arm.c (arm_elf_section_letter): Delete.
|
|
|
|
|
|
* config/tc-arm.h (md_elf_section_letter): Delete.
|
|
|
|
|
|
* doc/c-arm.texi (ARM Section Attribute): Delete section.
|
|
|
|
|
|
* testsuite/gas/arm/section-execute-only.d: Delete.
|
|
|
|
|
|
* testsuite/gas/arm/section-execute-only.s: Delete.
|
|
|
|
|
|
|
2016-02-04 17:55:10 +08:00
|
|
|
|
2016-02-04 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/19561
|
|
|
|
|
|
* config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2
|
|
|
|
|
|
to handle encoding of RRUX instruction.
|
|
|
|
|
|
* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
|
|
|
|
|
|
shift instructions.
|
|
|
|
|
|
* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
|
|
|
|
|
|
|
2016-02-02 22:11:38 +08:00
|
|
|
|
2016-02-03 Max Filippov <jcmvbkbc@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF*
|
|
|
|
|
|
substitutions for BFD_RELOC_* as unsigned.
|
2016-02-04 17:55:10 +08:00
|
|
|
|
* testsuite/gas/xtensa/all.exp: Add loc to list of xtensa tests.
|
|
|
|
|
|
* testsuite/gas/xtensa/loc.d: New file: loc test result patterns.
|
|
|
|
|
|
* testsuite/gas/xtensa/loc.s: New file: loc test.
|
2016-02-02 22:11:38 +08:00
|
|
|
|
|
msp430: Set DWARF2_ADDR_SIZE to 4.
This change makes gas's notion of the msp430 dwarf2 address size match
that of gcc and gdb. This is needed so that the format of addresses
generated for DW_LNE_set_address in .debug_line will match the address
size for the compilation unit.
In gcc/config/msp430/msp430.h, it's set to 4:
#define DWARF2_ADDR_SIZE 4
Likewise in gdb/msp430-tdep.c:
set_gdbarch_dwarf2_addr_size (gdbarch, 4);
(As far as I can tell, however, GDB doesn't use this value when decoding
.debug_line. Instead, GDB uses the Pointer Size from the compilation
unit.)
readelf is able to seamlessly handle mismatches between these various
sizes by using the size of the DW_LNE_set_address instruction to
determine the address size. Another way to fix this problem is to
make GDB behave in a similar manner. In my opinion, GDB should detect
and inform the user about these mismatches; it's not clear to me if
it's correct for GDB to go ahead and read the address anyway when a
size mismatch is detected.
Without this change, addresses in .debug_line are encoded in two bytes
for some multilibs. When GDB reads the address for
DW_LNE_set_address, it uses the pointer size provided by the CU. When
these values don't match, GDB reads the wrong number of bytes. In the
cases that I've looked at, GDB is reading 4 bytes from a 2 byte
container, which results in a garbage address. GDB discards lines
which have a bogus address; the end result is that GDB records no line
number information for CUs which have a mismatch between the address
size (from the CU) and the format of the address used by
DW_LNE_set_address.
gas/ChangeLog:
* config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
2016-01-28 03:44:38 +08:00
|
|
|
|
2016-02-03 Kevin Buettner <kevinb@redhat.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
|
msp430: Set DWARF2_ADDR_SIZE to 4.
This change makes gas's notion of the msp430 dwarf2 address size match
that of gcc and gdb. This is needed so that the format of addresses
generated for DW_LNE_set_address in .debug_line will match the address
size for the compilation unit.
In gcc/config/msp430/msp430.h, it's set to 4:
#define DWARF2_ADDR_SIZE 4
Likewise in gdb/msp430-tdep.c:
set_gdbarch_dwarf2_addr_size (gdbarch, 4);
(As far as I can tell, however, GDB doesn't use this value when decoding
.debug_line. Instead, GDB uses the Pointer Size from the compilation
unit.)
readelf is able to seamlessly handle mismatches between these various
sizes by using the size of the DW_LNE_set_address instruction to
determine the address size. Another way to fix this problem is to
make GDB behave in a similar manner. In my opinion, GDB should detect
and inform the user about these mismatches; it's not clear to me if
it's correct for GDB to go ahead and read the address anyway when a
size mismatch is detected.
Without this change, addresses in .debug_line are encoded in two bytes
for some multilibs. When GDB reads the address for
DW_LNE_set_address, it uses the pointer size provided by the CU. When
these values don't match, GDB reads the wrong number of bytes. In the
cases that I've looked at, GDB is reading 4 bytes from a 2 byte
container, which results in a garbage address. GDB discards lines
which have a bogus address; the end result is that GDB records no line
number information for CUs which have a mismatch between the address
size (from the CU) and the format of the address used by
DW_LNE_set_address.
gas/ChangeLog:
* config/tc-msp430.h (DWARF2_ADDR_SIZE): Set to 4.
2016-01-28 03:44:38 +08:00
|
|
|
|
|
2016-02-04 00:25:15 +08:00
|
|
|
|
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19520
|
|
|
|
|
|
* NEWS: Mention new command line option -mrelax-relocations and
|
|
|
|
|
|
new configure option --enable-x86-relax-relocations for x86
|
|
|
|
|
|
target.
|
|
|
|
|
|
* config.in: Regenerated.
|
|
|
|
|
|
* configure.ac: Add --enable-x86-relax-relocations.
|
|
|
|
|
|
(ac_default_x86_relax_relocations): New. Default to 1 except
|
|
|
|
|
|
for x86 Solaris targets older than Solaris 12.
|
|
|
|
|
|
(DEFAULT_GENERATE_X86_RELAX_RELOCATIONS): Define.
|
|
|
|
|
|
* configure: Likewise.
|
|
|
|
|
|
* config/tc-i386.c (generate_relax_relocations): New.
|
|
|
|
|
|
(OPTION_MRELAX_RELOCATIONS): Likewise.
|
|
|
|
|
|
(output_disp): Don't generate relax relocations if
|
|
|
|
|
|
generate_relax_relocations is 0.
|
|
|
|
|
|
(md_longopts): Add -mrelax-relocations.
|
|
|
|
|
|
(md_show_usage): Likewise.
|
|
|
|
|
|
(md_parse_option): Handle OPTION_MRELAX_RELOCATIONS.
|
|
|
|
|
|
* doc/c-i386.texi: Document -mrelax-relocations=.
|
|
|
|
|
|
* testsuite/gas/i386/got-no-relax.d: New file.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-gotpcrel-no-relax.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/got.d: Pass -mrelax-relocations=yes to as.
|
|
|
|
|
|
* testsuite/gas/i386/localpic.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/reloc32.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-gotpcrel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-gotpcrel.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/i386.exp: Run got-no-relax and
|
|
|
|
|
|
x86-64-gotpcrel-no-relax.
|
|
|
|
|
|
|
2016-02-03 22:42:39 +08:00
|
|
|
|
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Mention new command line option -mfence-as-lock-add=yes
|
|
|
|
|
|
for x86 target.
|
|
|
|
|
|
|
2016-02-03 22:37:21 +08:00
|
|
|
|
2016-02-03 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Remove duplicated marker for 2.26.
|
|
|
|
|
|
|
2016-02-02 23:52:42 +08:00
|
|
|
|
2016-02-02 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/thumb2_it_search.d: Skip non-elf targets.
|
|
|
|
|
|
|
2016-02-02 00:31:35 +08:00
|
|
|
|
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ip2k/allinsn.d: New file.
|
|
|
|
|
|
* testsuite/gas/ip2k/allinsn.s: New file.
|
|
|
|
|
|
* testsuite/gas/ip2k/ip2k-allinsn.exp: New file.
|
|
|
|
|
|
|
2016-02-02 04:21:19 +08:00
|
|
|
|
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
|
|
|
|
|
|
some load instructions.
|
|
|
|
|
|
* testsuite/gas/epiphany/allinsn.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/epiphany/regression.d: Likewise.
|
|
|
|
|
|
|
2016-02-02 04:01:52 +08:00
|
|
|
|
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l'
|
|
|
|
|
|
suffixes from instruction mnemonics in expected output.
|
|
|
|
|
|
* testsuite/gas/epiphany/allinsn.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/epiphany/regression.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/epiphany/sample.d: Likewise.
|
|
|
|
|
|
|
2016-02-02 03:20:25 +08:00
|
|
|
|
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/epiphany/addr-syntax.d: Update expected register
|
|
|
|
|
|
names.
|
|
|
|
|
|
* testsuite/gas/epiphany/allinsn.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/epiphany/sample.d: Likewise.
|
|
|
|
|
|
|
2016-02-02 02:21:37 +08:00
|
|
|
|
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/epiphany/sample.d: Update expected output.
|
|
|
|
|
|
|
2016-02-02 01:03:56 +08:00
|
|
|
|
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
2016-04-07 21:43:14 +08:00
|
|
|
|
* config/tc-arc.c (md_apply_fix): Allow addendum.
|
|
|
|
|
|
(arc_reloc_op): Allow complex expressions for tpoff.
|
|
|
|
|
|
(md_apply_fix): Handle resolved TLS local symbol.
|
2016-02-02 01:03:56 +08:00
|
|
|
|
* testsuite/gas/arc/tls-relocs1.d: New file.
|
|
|
|
|
|
* testsuite/gas/arc/tls-relocs1.s: Likewise.
|
|
|
|
|
|
|
2016-02-01 22:32:25 +08:00
|
|
|
|
2016-02-01 Loria <Loria@phantasia.org>
|
|
|
|
|
|
|
|
|
|
|
|
PR target/19311
|
|
|
|
|
|
* config/tc-arm.c (encode_arm_immediate): Recode to improve
|
|
|
|
|
|
efficiency and avoid an LLVM loop optimization bug.
|
|
|
|
|
|
|
2016-02-01 19:36:59 +08:00
|
|
|
|
2016-02-01 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-microblaze.c (parse_imm): Fix compile time warning
|
|
|
|
|
|
message extending a negative 32-bit value into a larger signed
|
|
|
|
|
|
value on a 32-bit host.
|
|
|
|
|
|
|
2016-01-29 23:47:45 +08:00
|
|
|
|
2016-01-29 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19532
|
|
|
|
|
|
* configure.ac (compressed_debug_sections): Replace == with =.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
|
2016-01-29 20:46:50 +08:00
|
|
|
|
2016-01-29 Andrew Senkevich <andrew.senkevich@intel.com>
|
|
|
|
|
|
H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (avoid_fence): New.
|
|
|
|
|
|
(output_insn): Encode as lock addl $0x0, (%{r,e}sp) if avoid_fence
|
|
|
|
|
|
is true.
|
|
|
|
|
|
(OPTION_FENCE_AS_LOCK_ADD): New.
|
|
|
|
|
|
(md_longopts): Add -mfence-as-lock-add.
|
|
|
|
|
|
(md_parse_option): Handle -mfence-as-lock-add.
|
|
|
|
|
|
(md_show_usage): Add -mfence-as-lock-add=[no|yes].
|
|
|
|
|
|
* doc/c-i386.texi (-mfence-as-lock-add): Document.
|
2016-01-29 21:01:07 +08:00
|
|
|
|
* testsuite/gas/i386/i386.exp: Run new tests.
|
|
|
|
|
|
* testsuite/gas/i386/fence-as-lock-add.s: New.
|
|
|
|
|
|
* testsuite/gas/i386/fence-as-lock-add-yes.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/fence-as-lock-add-no.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-fence-as-lock-add-yes.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/i386/x86-64-fence-as-lock-add-no.d: Likewise.
|
2016-01-29 20:46:50 +08:00
|
|
|
|
|
2016-01-28 02:24:51 +08:00
|
|
|
|
2016-01-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.ac (compressed_debug_sections): Remove trailing `]'.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
|
2016-01-26 09:01:11 +08:00
|
|
|
|
2016-01-25 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (OPTION_OMIT_LOCK_PREFIX): Renamed to ...
|
|
|
|
|
|
(OPTION_MOMIT_LOCK_PREFIX): This.
|
|
|
|
|
|
(md_longopts): Updated.
|
|
|
|
|
|
(md_parse_option): Likewise.
|
|
|
|
|
|
|
2016-01-26 04:39:40 +08:00
|
|
|
|
2016-01-25 Catherine Moore <clm@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/mips/tc-mips.c (md_begin): Avoid gp-relative addressing
|
|
|
|
|
|
if abicalls are in effect.
|
|
|
|
|
|
* testsuite/gas/mips/sdata-gp.s: New test.
|
|
|
|
|
|
* testsuite/gas/mips/sdata-gp.d: New expected output
|
|
|
|
|
|
* testsuite/gas/mips/mips.exp: Run new test.
|
|
|
|
|
|
|
2016-01-25 23:06:54 +08:00
|
|
|
|
2016-01-25 Renlin Li <renlin.li@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/thumb2_it_search.d: New.
|
|
|
|
|
|
* testsuite/gas/arm/thumb2_it_search.s: New.
|
|
|
|
|
|
|
2016-01-21 22:39:34 +08:00
|
|
|
|
2016-01-21 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/19454
|
|
|
|
|
|
* testsuite/gas/arm/mapshort-elf.d: Fix expected output to cope
|
|
|
|
|
|
with arm-netbsdelf target.
|
|
|
|
|
|
* testsuite/gas/arm/blx-bl-convert.d: Skip for netbsdelf.
|
|
|
|
|
|
|
2016-01-20 23:00:57 +08:00
|
|
|
|
2016-01-20 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
2016-01-21 01:02:42 +08:00
|
|
|
|
PR 19456
|
|
|
|
|
|
* testsuite/gas/arm/weakdef-1.d: Skip for VxWorks.
|
|
|
|
|
|
* testsuite/gas/arm/blx-bl-convert.d
|
|
|
|
|
|
* testsuite/gas/arm/plt-1.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/reloc-bad.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/thumb-w-good.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/thumb2_pool.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/ldconst.d: Adjust so that it works with VxWorks
|
|
|
|
|
|
* testsuite/gas/arm/tls_vxworks.d: Update expected output.
|
|
|
|
|
|
|
2016-01-21 00:21:34 +08:00
|
|
|
|
PR 19499
|
|
|
|
|
|
* doc/as.texinfo (Errors): Correct documentation describing the
|
|
|
|
|
|
interaction of .file and .line with warning and error messages.
|
|
|
|
|
|
|
2016-01-20 23:00:57 +08:00
|
|
|
|
PR 19458
|
|
|
|
|
|
* testsuite/gas/arm/armv8_2-a.d: Skip for COFF based targets.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-main.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/arm/archv8m-base.d: Likewise.
|
|
|
|
|
|
|
2016-01-20 22:25:46 +08:00
|
|
|
|
2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/aarch64/armv8_2-a-illegal.d: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/armv8_2-a-illegal.l: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/armv8_2-a-illegal.s: New.
|
|
|
|
|
|
|
2016-01-20 20:53:50 +08:00
|
|
|
|
2016-01-20 Mickael Guene <mickael.guene@st.com>
|
|
|
|
|
|
Terry Guo <terry.guo@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/obj-elf.c (obj_elf_change_section) : Allow arm section with
|
|
|
|
|
|
SHF_ARM_NOREAD section flag.
|
|
|
|
|
|
* config/tc-arm.h (md_elf_section_letter) : Implement this hook to
|
|
|
|
|
|
handle letter 'y'.
|
|
|
|
|
|
(arm_elf_section_letter) : Declare it.
|
|
|
|
|
|
* config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set
|
|
|
|
|
|
SHF_ARM_NOREAD section flag.
|
|
|
|
|
|
* doc/c-arm.texi (ARM section attribute): Document the 'y' attribute.
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/arm/section-execute-only.s: New test case.
|
|
|
|
|
|
* testsuite/gas/arm/section-execute-only.d: Expected output.
|
|
|
|
|
|
|
MIPS: Remove remnants of 48-bit microMIPS instruction support
The POOL48A major opcode was defined in early revisions of the 64-bit
microMIPS ISA, has never been implemented, and was removed before the
64-bit microMIPS ISA specification[1] has been finalized.
This complements commit a6c7053929dd ("MIPS/opcodes: Remove microMIPS
48-bit LI instruction").
References:
[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of
Major Opcode Field", p. 578
gas/
* config/tc-mips.c (micromips_insn_length): Remove the mention
of 48-bit microMIPS instructions.
gdb/
* mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS
instruction support.
(micromips_next_pc): Likewise.
(micromips_scan_prologue): Likewise.
(micromips_deal_with_atomic_sequence): Likewise.
(micromips_stack_frame_destroyed_p): Likewise.
(mips_breakpoint_from_pc): Likewise.
opcodes/
* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
instruction support.
2016-01-19 05:29:37 +08:00
|
|
|
|
2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (micromips_insn_length): Remove the mention
|
|
|
|
|
|
of 48-bit microMIPS instructions.
|
|
|
|
|
|
|
2016-01-18 13:36:49 +08:00
|
|
|
|
2016-01-18 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2016-01-17 09:50:55 +08:00
|
|
|
|
2016-01-17 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2016-01-17 09:43:43 +08:00
|
|
|
|
2016-01-17 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/cfi/cfi.exp: Exclude m68hc11/12 from m68k test.
|
|
|
|
|
|
|
2016-01-15 00:23:35 +08:00
|
|
|
|
2016-01-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/rl78/sp-relative-movw.s: New test.
|
|
|
|
|
|
* testsuite/gas/rl78/sp-relative-movw.d: Expected disassembly.
|
|
|
|
|
|
* testsuite/gas/rl78/rl78.exp: Run the new test.
|
|
|
|
|
|
|
2016-01-14 18:55:11 +08:00
|
|
|
|
2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/aarch64/illegal-sysreg-2.l: New.
|
|
|
|
|
|
* testsuite/gas/aarch64/illegal-sysreg-2.d: New.
|
|
|
|
|
|
|
2016-01-14 04:58:29 +08:00
|
|
|
|
2016-01-13 Maciej W. Rozycki <macro@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nios2.c (output_movia): Preset `code' to 0.
|
|
|
|
|
|
|
2016-01-14 01:47:34 +08:00
|
|
|
|
2016-01-13 Yoshinori Sato <ysato@users.sourceforge.jp>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-h8300.c (get_operand): Remove spurious condition in
|
|
|
|
|
|
test for closing parenthesis.
|
|
|
|
|
|
|
2016-01-13 00:35:30 +08:00
|
|
|
|
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_ext_v8_2): New.
|
|
|
|
|
|
(insns): Add "esb".
|
|
|
|
|
|
* testsuite/gas/arm/armv8_2-a.d: New.
|
|
|
|
|
|
* testsuite/gas/arm/armv8_2-a.s: New.
|
|
|
|
|
|
|
2016-01-12 15:50:26 +08:00
|
|
|
|
2016-01-12 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/vsx3.d: Accept nop padding.
|
|
|
|
|
|
|
2016-01-12 01:54:58 +08:00
|
|
|
|
2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* testsuite/gas/ppc/power9.d <xscmpnedp, xvcmpnedp, xvcmpnedp.,
|
|
|
|
|
|
xvcmpnesp, xvcmpnesp.>: Delete tests.
|
|
|
|
|
|
* testsuite/gas/ppc/power9.s: Likewise.
|
|
|
|
|
|
* testsuite/gas/ppc/vsx3.d: Likewise.
|
|
|
|
|
|
* testsuite/gas/ppc/vsx3.s: Likewise.
|
|
|
|
|
|
|
2016-01-08 18:38:00 +08:00
|
|
|
|
2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
|
|
|
|
|
|
|
|
|
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PR gas/13050
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* testsuite/gas/m68k/all.exp: Add tests p13050-1 and p13050-2.
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* testsuite/gas/m68k/p13050-1.s: New file.
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* testsuite/gas/m68k/p13050-2.d: New file.
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* testsuite/gas/m68k/p13050-2.s: New file.
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2016-01-05 22:46:39 +08:00
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2016-01-06 Andrew Burgess <andrew.burgess@embecosm.com>
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* testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names.
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* testsuite/gas/arc/add.d: Likewise.
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* testsuite/gas/arc/and.d: Likewise.
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* testsuite/gas/arc/asl.d: Likewise.
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* testsuite/gas/arc/asr.d: Likewise.
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* testsuite/gas/arc/bic.d: Likewise.
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* testsuite/gas/arc/extb.d: Likewise.
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* testsuite/gas/arc/extw.d: Likewise.
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* testsuite/gas/arc/j.d: Likewise.
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* testsuite/gas/arc/jl.d: Likewise.
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* testsuite/gas/arc/ld2.d: Likewise.
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* testsuite/gas/arc/lsr.d: Likewise.
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* testsuite/gas/arc/mov.d: Likewise.
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* testsuite/gas/arc/or.d: Likewise.
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* testsuite/gas/arc/pcl-relocs.d: Likewise.
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* testsuite/gas/arc/pcrel-relocs.d: Likewise.
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* testsuite/gas/arc/pic-relocs.d: Likewise.
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* testsuite/gas/arc/plt-relocs.d: Likewise.
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* testsuite/gas/arc/rlc.d: Likewise.
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* testsuite/gas/arc/ror.d: Likewise.
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* testsuite/gas/arc/rrc.d: Likewise.
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* testsuite/gas/arc/sbc.d: Likewise.
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* testsuite/gas/arc/sda-relocs.d: Likewise.
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* testsuite/gas/arc/sda-relocs2.d: Likewise.
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* testsuite/gas/arc/sexb.d: Likewise.
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* testsuite/gas/arc/sexw.d: Likewise.
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* testsuite/gas/arc/st.d: Likewise.
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* testsuite/gas/arc/sub.d: Likewise.
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* testsuite/gas/arc/tls-relocs.d: Likewise.
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* testsuite/gas/arc/xor.d: Likewise.
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2016-01-01 19:25:12 +08:00
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2016-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2016-01-01 18:44:31 +08:00
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For older changes see ChangeLog-2015 and testsuite/ChangeLog-2015
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Copyright (C) 2016 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
|
