binutils-gdb/sim/testsuite/cr16/orw.cgs

# cr16 testcase for orw reg, reg
# mach(): cr16

	.include "testutils.inc"

	start

	.global orw
orw:
	movw $3, r4
	movw $6, r5

	orw r4, r5

	test_h_gr r5, 7

	pass
Update testcase comment. addb.cgs addd.cgs addi.cgs andb.cgs andd.cgs andw.cgs ashub.cgs ashub_i.cgs ashud.cgs ashud_i.cgs ashuw.cgs ashuw_i.cgs cmpi.cgs cmpw.cgs jlt.cgs jump.cgs loadd.cgs loadw.cgs lshb.cgs lshb_i.cgs lshd.cgs lshd_i.cgs lshw.cgs lshw_i.cgs movb.cgs movd.cgs movw.cgs movxb.cgs movxw.cgs movzb.cgs movzw.cgs mulb.cgs muluw.cgs mulw.cgs orb.cgs ord.cgs orw.cgs pop1.cgs pop2.cgs pop3.cgs popret1.cgs popret2.cgs popret3.cgs push1.cgs push2.cgs push3.cgs Added BIT operation testcases: cbitb.cgs cbitw.cgs sbitb.cgs sbitw.cgs tbitb.cgs tbit.cgs and tbitw.cgs 2008-05-05 17:52:46 +08:00			`# cr16 testcase for orw reg, reg`
New files: Testcases for cr16 instruction set. 2008-04-08 17:07:02 +08:00			`# mach(): cr16`

			`.include "testutils.inc"`

			`start`

Update testcase comment. addb.cgs addd.cgs addi.cgs andb.cgs andd.cgs andw.cgs ashub.cgs ashub_i.cgs ashud.cgs ashud_i.cgs ashuw.cgs ashuw_i.cgs cmpi.cgs cmpw.cgs jlt.cgs jump.cgs loadd.cgs loadw.cgs lshb.cgs lshb_i.cgs lshd.cgs lshd_i.cgs lshw.cgs lshw_i.cgs movb.cgs movd.cgs movw.cgs movxb.cgs movxw.cgs movzb.cgs movzw.cgs mulb.cgs muluw.cgs mulw.cgs orb.cgs ord.cgs orw.cgs pop1.cgs pop2.cgs pop3.cgs popret1.cgs popret2.cgs popret3.cgs push1.cgs push2.cgs push3.cgs Added BIT operation testcases: cbitb.cgs cbitw.cgs sbitb.cgs sbitw.cgs tbitb.cgs tbit.cgs and tbitw.cgs 2008-05-05 17:52:46 +08:00			`.global orw`
			`orw:`
New files: Testcases for cr16 instruction set. 2008-04-08 17:07:02 +08:00			`movw $3, r4`
			`movw $6, r5`

			`orw r4, r5`

			`test_h_gr r5, 7`

			`pass`