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83 lines
1.4 KiB
ArmAsm
83 lines
1.4 KiB
ArmAsm
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//Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp
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// Spec Reference: ldimmhalf l dreg
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS -1;
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// test Dreg
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R0.L = 0x0001;
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R1.L = 0x0003;
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R2.L = 0x0005;
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R3.L = 0x0007;
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R4.L = 0x0009;
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R5.L = 0x000b;
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R6.L = 0x000d;
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R7.L = 0x000f;
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CHECKREG r0, 0xffff0001;
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CHECKREG r1, 0xffff0003;
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CHECKREG r2, 0xffff0005;
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CHECKREG r3, 0xffff0007;
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CHECKREG r4, 0xffff0009;
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CHECKREG r5, 0xffff000b;
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CHECKREG r6, 0xffff000d;
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CHECKREG r7, 0xffff000f;
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R0.L = 0x0010;
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R1.L = 0x0030;
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R2.L = 0x0050;
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R3.L = 0x0070;
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R4.L = 0x0090;
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R5.L = 0x00b0;
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R6.L = 0x00d0;
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R7.L = 0x00f0;
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CHECKREG r0, 0xffff0010;
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CHECKREG r1, 0xffff0030;
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CHECKREG r2, 0xffff0050;
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CHECKREG r3, 0xffff0070;
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CHECKREG r4, 0xffff0090;
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CHECKREG r5, 0xffff00b0;
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CHECKREG r6, 0xffff00d0;
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CHECKREG r7, 0xffff00f0;
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R0.L = 0x0100;
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R1.L = 0x0300;
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R2.L = 0x0500;
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R3.L = 0x0700;
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R4.L = 0x0900;
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R5.L = 0x0b00;
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R6.L = 0x0d00;
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R7.L = 0x0f00;
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CHECKREG r0, 0xffff0100;
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CHECKREG r1, 0xffff0300;
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CHECKREG r2, 0xffff0500;
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CHECKREG r3, 0xffff0700;
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CHECKREG r4, 0xffff0900;
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CHECKREG r5, 0xffff0b00;
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CHECKREG r6, 0xffff0d00;
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CHECKREG r7, 0xffff0f00;
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R0.L = 0x1000;
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R1.L = 0x3000;
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R2.L = 0x5000;
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R3.L = 0x7000;
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R4.L = 0x9000;
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R5.L = 0xb000;
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R6.L = 0xd000;
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R7.L = 0xf000;
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CHECKREG r0, 0xffff1000;
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CHECKREG r1, 0xffff3000;
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CHECKREG r2, 0xffff5000;
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CHECKREG r3, 0xffff7000;
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CHECKREG r4, 0xffff9000;
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CHECKREG r5, 0xffffb000;
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CHECKREG r6, 0xffffd000;
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CHECKREG r7, 0xfffff000;
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pass
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