mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
211 lines
4.7 KiB
ArmAsm
211 lines
4.7 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp
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// Spec Reference: dsp32shift align24
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x00000001;
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imm32 r1, 0x01000801;
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imm32 r2, 0x08200802;
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imm32 r3, 0x08030803;
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imm32 r4, 0x08004804;
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imm32 r5, 0x08000505;
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imm32 r6, 0x08000866;
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imm32 r7, 0x08000807;
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R1 = ALIGN24 ( R1 , R0 );
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R2 = ALIGN24 ( R2 , R0 );
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R3 = ALIGN24 ( R3 , R0 );
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R4 = ALIGN24 ( R4 , R0 );
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R5 = ALIGN24 ( R5 , R0 );
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R6 = ALIGN24 ( R6 , R0 );
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R7 = ALIGN24 ( R7 , R0 );
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R0 = ALIGN24 ( R0 , R0 );
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CHECKREG r0, 0x00000100;
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CHECKREG r1, 0x00080100;
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CHECKREG r2, 0x20080200;
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CHECKREG r3, 0x03080300;
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CHECKREG r4, 0x00480400;
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CHECKREG r5, 0x00050500;
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CHECKREG r6, 0x00086600;
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CHECKREG r7, 0x00080700;
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imm32 r0, 0x0900d001;
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imm32 r1, 0x09000002;
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imm32 r2, 0x09400002;
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imm32 r3, 0x09100003;
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imm32 r4, 0x09020004;
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imm32 r5, 0x09003005;
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imm32 r6, 0x09000406;
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imm32 r7, 0x09000057;
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R0 = ALIGN24 ( R0 , R1 );
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R2 = ALIGN24 ( R2 , R1 );
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R3 = ALIGN24 ( R3 , R1 );
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R4 = ALIGN24 ( R4 , R1 );
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R5 = ALIGN24 ( R5 , R1 );
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R6 = ALIGN24 ( R6 , R1 );
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R7 = ALIGN24 ( R7 , R1 );
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R1 = ALIGN24 ( R1 , R1 );
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CHECKREG r0, 0x00D00109;
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CHECKREG r1, 0x00000209;
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CHECKREG r2, 0x40000209;
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CHECKREG r3, 0x10000309;
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CHECKREG r4, 0x02000409;
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CHECKREG r5, 0x00300509;
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CHECKREG r6, 0x00040609;
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CHECKREG r7, 0x00005709;
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imm32 r0, 0x0a00e001;
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imm32 r1, 0x0a00e001;
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imm32 r2, 0x0a00000f;
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imm32 r3, 0x0a400010;
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imm32 r4, 0x0a05e004;
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imm32 r5, 0x0a006005;
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imm32 r6, 0x0a00e706;
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imm32 r7, 0x0a00e087;
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R0 = ALIGN24 ( R0 , R2 );
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R1 = ALIGN24 ( R1 , R2 );
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R3 = ALIGN24 ( R3 , R2 );
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R4 = ALIGN24 ( R4 , R2 );
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R5 = ALIGN24 ( R5 , R2 );
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R6 = ALIGN24 ( R6 , R2 );
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R7 = ALIGN24 ( R7 , R2 );
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R2 = ALIGN24 ( R2 , R2 );
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CHECKREG r0, 0x00E0010A;
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CHECKREG r1, 0x00E0010A;
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CHECKREG r2, 0x00000F0A;
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CHECKREG r3, 0x4000100A;
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CHECKREG r4, 0x05E0040A;
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CHECKREG r5, 0x0060050A;
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CHECKREG r6, 0x00E7060A;
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CHECKREG r7, 0x00E0870A;
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imm32 r0, 0x2b00f001;
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imm32 r1, 0x0300f001;
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imm32 r2, 0x0b40f002;
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imm32 r3, 0x0b050010;
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imm32 r4, 0x0b006004;
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imm32 r5, 0x0b00f705;
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imm32 r6, 0x0b00f086;
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imm32 r7, 0x0b00f009;
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R0 = ALIGN24 ( R0 , R3 );
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R1 = ALIGN24 ( R1 , R3 );
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R2 = ALIGN24 ( R2 , R3 );
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R4 = ALIGN24 ( R4 , R3 );
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R5 = ALIGN24 ( R5 , R3 );
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R6 = ALIGN24 ( R6 , R3 );
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R7 = ALIGN24 ( R7 , R3 );
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R3 = ALIGN24 ( R3 , R3 );
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CHECKREG r0, 0x00F0010B;
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CHECKREG r1, 0x00F0010B;
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CHECKREG r2, 0x40F0020B;
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CHECKREG r3, 0x0500100B;
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CHECKREG r4, 0x0060040B;
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CHECKREG r5, 0x00F7050B;
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CHECKREG r6, 0x00F0860B;
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CHECKREG r7, 0x00F0090B;
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imm32 r0, 0x4c0000c0;
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imm32 r1, 0x050100c0;
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imm32 r2, 0x0c6200c0;
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imm32 r3, 0x0c0700c0;
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imm32 r4, 0x0c04800c;
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imm32 r5, 0x0c0509c0;
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imm32 r6, 0x0c060000;
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imm32 r7, 0x0c0700ca;
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R0 = ALIGN24 ( R0 , R4 );
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R1 = ALIGN24 ( R1 , R4 );
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R2 = ALIGN24 ( R2 , R4 );
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R3 = ALIGN24 ( R3 , R4 );
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R5 = ALIGN24 ( R5 , R4 );
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R6 = ALIGN24 ( R6 , R4 );
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R7 = ALIGN24 ( R7 , R4 );
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R4 = ALIGN24 ( R4 , R4 );
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CHECKREG r0, 0x0000C00C;
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CHECKREG r1, 0x0100C00C;
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CHECKREG r2, 0x6200C00C;
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CHECKREG r3, 0x0700C00C;
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CHECKREG r4, 0x04800C0C;
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CHECKREG r5, 0x0509C00C;
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CHECKREG r6, 0x0600000C;
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CHECKREG r7, 0x0700CA0C;
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imm32 r0, 0xa00100d0;
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imm32 r1, 0xa00100d1;
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imm32 r2, 0xa00200d0;
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imm32 r3, 0xa00300d0;
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imm32 r4, 0xa00400d0;
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imm32 r5, 0xa0050007;
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imm32 r6, 0xa00600d0;
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imm32 r7, 0xa00700d0;
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R0 = ALIGN24 ( R0 , R5 );
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R1 = ALIGN24 ( R1 , R5 );
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R2 = ALIGN24 ( R2 , R5 );
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R3 = ALIGN24 ( R3 , R5 );
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R4 = ALIGN24 ( R4 , R5 );
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R6 = ALIGN24 ( R6 , R5 );
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R7 = ALIGN24 ( R7 , R5 );
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R5 = ALIGN24 ( R5 , R5 );
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CHECKREG r0, 0x0100D0A0;
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CHECKREG r1, 0x0100D1A0;
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CHECKREG r2, 0x0200D0A0;
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CHECKREG r3, 0x0300D0A0;
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CHECKREG r4, 0x0400D0A0;
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CHECKREG r5, 0x050007A0;
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CHECKREG r6, 0x0600D0A0;
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CHECKREG r7, 0x0700D0A0;
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imm32 r0, 0xb2010000;
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imm32 r1, 0xb0310000;
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imm32 r2, 0xb042000f;
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imm32 r3, 0xbf030000;
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imm32 r4, 0xba040000;
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imm32 r5, 0xbb050000;
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imm32 r6, 0xbc060009;
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imm32 r7, 0xb0e70000;
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R0 = ALIGN24 ( R0 , R6 );
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R1 = ALIGN24 ( R1 , R6 );
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R2 = ALIGN24 ( R2 , R6 );
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R3 = ALIGN24 ( R3 , R6 );
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R4 = ALIGN24 ( R4 , R6 );
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R5 = ALIGN24 ( R5 , R6 );
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R6 = ALIGN24 ( R6 , R6 );
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R7 = ALIGN24 ( R7 , R6 );
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CHECKREG r0, 0x010000BC;
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CHECKREG r1, 0x310000BC;
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CHECKREG r2, 0x42000FBC;
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CHECKREG r3, 0x030000BC;
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CHECKREG r4, 0x040000BC;
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CHECKREG r5, 0x050000BC;
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CHECKREG r6, 0x060009BC;
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CHECKREG r7, 0xE7000006;
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imm32 r0, 0xd23100e0;
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imm32 r1, 0xd04500e0;
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imm32 r2, 0xde32f0e0;
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imm32 r3, 0xd90300e0;
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imm32 r4, 0xd07400e0;
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imm32 r5, 0xdef500e0;
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imm32 r6, 0xd06600e0;
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imm32 r7, 0xd0080023;
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R1 = ALIGN24 ( R0 , R7 );
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R2 = ALIGN24 ( R1 , R7 );
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R3 = ALIGN24 ( R2 , R7 );
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R4 = ALIGN24 ( R3 , R7 );
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R5 = ALIGN24 ( R4 , R7 );
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R6 = ALIGN24 ( R5 , R7 );
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R7 = ALIGN24 ( R6 , R7 );
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R0 = ALIGN24 ( R7 , R7 );
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CHECKREG r0, 0xD0D0D0D0;
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CHECKREG r1, 0x3100E0D0;
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CHECKREG r2, 0x00E0D0D0;
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CHECKREG r3, 0xE0D0D0D0;
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CHECKREG r4, 0xD0D0D0D0;
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CHECKREG r5, 0xD0D0D0D0;
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CHECKREG r6, 0xD0D0D0D0;
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CHECKREG r7, 0xD0D0D0D0;
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pass
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