2013-08-06 05:58:23 +08:00
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2013-08-05 John Tytgat <john@bass-software.com>
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* po/POTFILES.in: Regenerate.
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2013-08-06 00:11:07 +08:00
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2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
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Konrad Eisele <konrad@gaisler.com>
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* config/tc-sparc.c (sparc_arch_types): Add leon.
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(sparc_arch): Move sparc4 around and add leon.
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(sparc_target_format): Document -Aleon.
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* doc/c-sparc.texi: Likewise.
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2013-08-05 16:31:48 +08:00
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2013-08-05 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (mips_lookup_insn): Make length and opend signed.
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include/opcode/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Document new VU0 operand characters.
(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
(OP_REG_R5900_ACC): New mips_reg_operand_types.
(INSN2_VU0_CHANNEL_SUFFIX): New macro.
(mips_vu0_channel_mask): Declare.
opcodes/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(print_vu0_channel): New function.
(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(print_insn_args): Handle '#'.
(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
* mips-opc.c (mips_vu0_channel_mask): New constant.
(decode_mips_operand): Handle new VU0 operand types.
(VU0, VU0CH): New macros.
(mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
Use "+6" rather than "G" for QMFC2 and QMTC2.
gas/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
(RWARN): Bump to 0x8000000.
(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
(RTYPE_R5900_ACC): New register types.
(RTYPE_MASK): Include them.
(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
macros.
(reg_names): Include them.
(mips_parse_register_1): New function, split out from...
(mips_parse_register): ...here. Add a channels_ptr parameter.
Look for VU0 channel suffixes when nonnull.
(reg_lookup): Update the call to mips_parse_register.
(mips_parse_vu0_channels): New function.
(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
(mips_operand_token): Add a "channels" field to the union.
Extend the comment above "ch" to OT_DOUBLE_CHAR.
(mips_parse_base_start): Match -- and ++. Handle channel suffixes.
(mips_parse_argument_token): Handle channel suffixes here too.
(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
Handle '#' formats.
(md_begin): Register $vfN and $vfI registers.
(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(match_vu0_suffix_operand): New function.
(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
(mips_lookup_insn): New function.
(mips_ip): Use it. Allow "+K" operands to be elided at the end
of an instruction. Handle '#' sequences.
gas/testsuite/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
coprocessor registers.
* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
* gas/mips/mips.exp: Run them.
2013-08-04 15:31:39 +08:00
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2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
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Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
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(RWARN): Bump to 0x8000000.
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(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
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(RTYPE_R5900_ACC): New register types.
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(RTYPE_MASK): Include them.
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(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
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macros.
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(reg_names): Include them.
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(mips_parse_register_1): New function, split out from...
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(mips_parse_register): ...here. Add a channels_ptr parameter.
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Look for VU0 channel suffixes when nonnull.
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(reg_lookup): Update the call to mips_parse_register.
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(mips_parse_vu0_channels): New function.
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(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
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(mips_operand_token): Add a "channels" field to the union.
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Extend the comment above "ch" to OT_DOUBLE_CHAR.
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(mips_parse_base_start): Match -- and ++. Handle channel suffixes.
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(mips_parse_argument_token): Handle channel suffixes here too.
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(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
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Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
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Handle '#' formats.
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(md_begin): Register $vfN and $vfI registers.
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(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
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(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
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OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
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(match_vu0_suffix_operand): New function.
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(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
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(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
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(mips_lookup_insn): New function.
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(mips_ip): Use it. Allow "+K" operands to be elided at the end
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of an instruction. Handle '#' sequences.
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2013-08-03 19:11:46 +08:00
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2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (macro, mips16_macro): Create an array of operand
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values and use it instead of sreg, treg, xreg, etc.
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2013-08-03 18:49:48 +08:00
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2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (match_int_operand): Use mips_int_operand_min
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and mips_int_operand_max.
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(mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
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Delete.
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(mips16_immed_operand, mips16_immed_in_range_p): New functions.
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(mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand
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instead of mips16_immed_operand.
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2013-08-03 18:41:13 +08:00
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2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (mips16_macro): Don't use move_register.
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(mips16_ip): Allow macros to use 'p'.
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include/opcode/
* mips.h (mips_decode_reg_operand): New function.
(INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
(INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
(INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
New macros.
(INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
(INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
(INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
(INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
(INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
(INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
(INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
(INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
(INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
macros to cover the gaps.
(INSN2_MOD_SP): Replace with...
(INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
(MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
(MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
(MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
(MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
Delete.
opcodes/
* mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
New macros.
(WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
(WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
(mips_builtin_opcodes): Use the new position-based read-write flags
instead of field-based ones. Use UDI for "udi..." instructions.
* mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
New macros.
(WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
(RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
(WR_SP, RD_16): New macros.
(RD_SP): Redefine as an INSN2_* flag.
(MOD_SP): Redefine in terms of RD_SP and WR_SP.
(mips16_opcodes): Use the new position-based read-write flags
instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
pinfo2 field.
* micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
New macros.
(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
(WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
(WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
(RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
(micromips_opcodes): Use the new position-based read-write flags
instead of field-based ones.
* mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
(print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
of field-based flags.
gas/
* config/tc-mips.c (MAX_OPERANDS): New macro.
(mips_operand_array): New structure.
(mips_operands, mips16_operands, micromips_operands): New arrays.
(micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map)
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map)
(micromips_to_32_reg_q_map): Delete.
(insn_operands, insn_opno, insn_extract_operand): New functions.
(validate_mips_insn): Take a mips_operand_array as argument and
use it to build up a list of operands. Extend to handle INSN_MACRO
and MIPS16.
(validate_mips16_insn): New function.
(validate_micromips_insn): Take a mips_operand_array as argument.
Handle INSN_MACRO.
(md_begin): Initialize mips_operands, mips16_operands and
micromips_operands. Call validate_mips_insn and
validate_micromips_insn for macro instructions too.
Call validate_mips16_insn for MIPS16 instructions.
(insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask):
New functions.
(gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use
them. Handle INSN_UDI.
(get_append_method): Use gpr_read_mask.
2013-08-02 04:55:25 +08:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (MAX_OPERANDS): New macro.
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(mips_operand_array): New structure.
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(mips_operands, mips16_operands, micromips_operands): New arrays.
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(micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
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(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map)
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(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map)
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(micromips_to_32_reg_q_map): Delete.
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(insn_operands, insn_opno, insn_extract_operand): New functions.
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(validate_mips_insn): Take a mips_operand_array as argument and
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use it to build up a list of operands. Extend to handle INSN_MACRO
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and MIPS16.
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(validate_mips16_insn): New function.
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(validate_micromips_insn): Take a mips_operand_array as argument.
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Handle INSN_MACRO.
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(md_begin): Initialize mips_operands, mips16_operands and
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micromips_operands. Call validate_mips_insn and
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validate_micromips_insn for macro instructions too.
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Call validate_mips16_insn for MIPS16 instructions.
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(insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask):
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New functions.
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(gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use
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them. Handle INSN_UDI.
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(get_append_method): Use gpr_read_mask.
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2013-08-02 04:40:24 +08:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
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flags for MIPS16 and non-MIPS16 instructions.
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(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
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(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
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(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
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(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
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and non-MIPS16 instructions. Fix formatting.
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2013-08-02 04:32:59 +08:00
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (reg_needs_delay): Move later in file.
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Use gpr_write_mask.
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(insns_between): Use gpr_read_mask instead of EXTRACT_OPERAND.
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Add Intel AVX-512 support
binutils/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
numeration in comments.
(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
dwarf table.
gas/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386-intel.c (O_zmmword_ptr): New.
(i386_types): Add zmmword.
(i386_intel_simplify_register): Allow regzmm.
(i386_intel_simplify): Handle zmmwords.
(i386_intel_operand): Handle RC/SAE, vector operations and
zmmwords.
* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
(struct RC_Operation): New.
(struct Mask_Operation): New.
(struct Broadcast_Operation): New.
(vex_prefix): Size of bytes increased to 4 to support EVEX
encoding.
(enum i386_error): Add new error codes: unsupported_broadcast,
broadcast_not_on_src_operand, broadcast_needed,
unsupported_masking, mask_not_on_destination, no_default_mask,
unsupported_rc_sae, rc_sae_operand_not_last_imm,
invalid_register_operand, try_vector_disp8.
(struct _i386_insn): Add new fields vrex, need_vrex, mask,
rounding, broadcast, memshift.
(struct RC_name): New.
(RC_NamesTable): New.
(evexlig): New.
(evexwig): New.
(extra_symbol_chars): Add '{'.
(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
(i386_operand_type): Add regzmm, regmask and vec_disp8.
(match_mem_size): Handle zmmwords.
(operand_type_match): Handle zmm-registers.
(mode_from_disp_size): Handle vec_disp8.
(fits_in_vec_disp8): New.
(md_begin): Handle {} properly.
(type_names): Add "rZMM", "Mask reg" and "Vector d8".
(build_vex_prefix): Handle vrex.
(build_evex_prefix): New.
(process_immext): Adjust to properly handle EVEX.
(md_assemble): Add EVEX encoding support.
(swap_2_operands): Correctly handle operands with masking,
broadcasting or RC/SAE.
(check_VecOperands): Support EVEX features.
(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
(match_template): Support regzmm and handle new error codes.
(process_suffix): Handle zmmwords and zmm-registers.
(check_byte_reg): Extend to zmm-registers.
(process_operands): Extend to zmm-registers.
(build_modrm_byte): Handle EVEX.
(output_insn): Adjust to properly handle EVEX case.
(disp_size): Handle vec_disp8.
(output_disp): Support compressed disp8*N evex feature.
(output_imm): Handle RC/SAE immediates properly.
(check_VecOperations): New.
(i386_immediate): Handle EVEX features.
(i386_index_check): Handle zmmwords and zmm-registers.
(RC_SAE_immediate): New.
(i386_att_operand): Handle EVEX features.
(parse_real_register): Add a check for ZMM/Mask registers.
(OPTION_MEVEXLIG): New.
(OPTION_MEVEXWIG): New.
(md_longopts): Add mevexlig and mevexwig.
(md_parse_option): Handle mevexlig and mevexwig options.
(md_show_usage): Add description for mevexlig and mevexwig.
* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
gas/testsuite/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/cfi/cfi-i386.s: Add tests for k0-k7.
* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
* gas/i386/intel-regs.d: Change correspondingly.
* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
* gas/i386/prefetch.d: Ditto.
* gas/i386/x86-64-prefetch-intel.d: Ditto.
* gas/i386/x86-64-prefetch.d: Ditto.
* gas/i386/avx512f-intel.d: New.
* gas/i386/avx512f-nondef.d: New.
* gas/i386/avx512f-nondef.s: New.
* gas/i386/avx512f-opts-intel.d: New.
* gas/i386/avx512f-opts.d: New.
* gas/i386/avx512f-opts.s: New.
* gas/i386/avx512f.d: New.
* gas/i386/avx512f.s: New.
* gas/i386/avx512cd-intel.d: New.
* gas/i386/avx512cd.d: New.
* gas/i386/avx512cd.s: New.
* gas/i386/avx512er-intel.d: New.
* gas/i386/avx512er.d: New.
* gas/i386/avx512er.s: New.
* gas/i386/avx512pf-intel.d: New.
* gas/i386/avx512pf.d: New.
* gas/i386/avx512pf.s: New.
* gas/i386/evex-lig.s: New.
* gas/i386/evex-lig256-intel.d: New.
* gas/i386/evex-lig256.d: New.
* gas/i386/evex-lig512-intel.d: New.
* gas/i386/evex-lig512.d: New.
* gas/i386/evex-wig.s: New.
* gas/i386/evex-wig1-intel.d: New.
* gas/i386/evex-wig1.d: New.
* gas/i386/inval-avx512f.l: New.
* gas/i386/inval-avx512f.s: New.
* gas/i386/x86-64-avx512f-intel.d: New.
* gas/i386/x86-64-avx512f-nondef.d: New.
* gas/i386/x86-64-avx512f-nondef.s: New.
* gas/i386/x86-64-avx512f-opts-intel.d: New.
* gas/i386/x86-64-avx512f-opts.d: New.
* gas/i386/x86-64-avx512f-opts.s: New.
* gas/i386/x86-64-avx512f.d: New.
* gas/i386/x86-64-avx512f.s: New.
* gas/i386/x86-64-avx512cd-intel.d: New.
* gas/i386/x86-64-avx512cd.d: New.
* gas/i386/x86-64-avx512cd.s: New.
* gas/i386/x86-64-avx512er-intel.d: New.
* gas/i386/x86-64-avx512er.d: New.
* gas/i386/x86-64-avx512er.s: New.
* gas/i386/x86-64-avx512pf-intel.d: New.
* gas/i386/x86-64-avx512pf.d: New.
* gas/i386/x86-64-avx512pf.s: New.
* gas/i386/x86-64-evex-lig.s: New.
* gas/i386/x86-64-evex-lig256-intel.d: New.
* gas/i386/x86-64-evex-lig256.d: New.
* gas/i386/x86-64-evex-lig512-intel.d: New.
* gas/i386/x86-64-evex-lig512.d: New.
* gas/i386/x86-64-evex-wig.s: New.
* gas/i386/x86-64-evex-wig1-intel.d: New.
* gas/i386/x86-64-evex-wig1.d: New.
* gas/i386/x86-64-inval-avx512f.l: New.
* gas/i386/x86-64-inval-avx512f.s: New.
* gas/i386/i386.exp: Run new AVX-512 tests.
opcodes/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis-evex.h: New.
* i386-dis.c (OP_Rounding): New.
(VPCMP_Fixup): New.
(OP_Mask): New.
(Rdq): New.
(XMxmmq): New.
(EXdScalarS): New.
(EXymm): New.
(EXEvexHalfBcstXmmq): New.
(EXxmm_mdq): New.
(EXEvexXGscat): New.
(EXEvexXNoBcst): New.
(VPCMP): New.
(EXxEVexR): New.
(EXxEVexS): New.
(XMask): New.
(MaskG): New.
(MaskE): New.
(MaskR): New.
(MaskVex): New.
(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
evex_rounding_mode, evex_sae_mode, mask_mode.
(USE_EVEX_TABLE): New.
(EVEX_TABLE): New.
(EVEX enum): New.
(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
REG_EVEX_0F38C7.
(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
MOD_EVEX_0F38C7_REG_6.
(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A55.
(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0.
(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
(struct vex): Add fields evex, r, v, mask_register_specifier,
zeroing, ll, b.
(intel_names_xmm): Add upper 16 registers.
(att_names_xmm): Ditto.
(intel_names_ymm): Ditto.
(att_names_ymm): Ditto.
(names_zmm): New.
(intel_names_zmm): Ditto.
(att_names_zmm): Ditto.
(names_mask): Ditto.
(intel_names_mask): Ditto.
(att_names_mask): Ditto.
(names_rounding): Ditto.
(names_broadcast): Ditto.
(x86_64_table): Add escape to evex-table.
(reg_table): Include reg_table evex-entries from
i386-dis-evex.h. Fix prefetchwt1 instruction.
(prefix_table): Add entries for new instructions.
(vex_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(mod_table): Ditto.
(get_valid_dis386): Properly handle new instructions.
(print_insn): Handle zmm and mask registers, print mask operand.
(intel_operand_size): Support EVEX, new modes and sizes.
(OP_E_register): Handle new modes.
(OP_E_memory): Ditto.
(OP_G): Ditto.
(OP_XMM): Ditto.
(OP_EX): Ditto.
(OP_VEX): Ditto.
* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
CpuAVX512PF and CpuVREX.
(operand_type_init): Add OPERAND_TYPE_REGZMM,
OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
StaticRounding, SAE, Disp8MemShift, NoDefMask.
(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
* i386-init.h: Regenerate.
* i386-opc.h (CpuAVX512F): New.
(CpuAVX512CD): New.
(CpuAVX512ER): New.
(CpuAVX512PF): New.
(CpuVREX): New.
(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
cpuavx512pf and cpuvrex fields.
(VecSIB): Add VecSIB512.
(EVex): New.
(Masking): New.
(VecESize): New.
(Broadcast): New.
(StaticRounding): New.
(SAE): New.
(Disp8MemShift): New.
(NoDefMask): New.
(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
staticrounding, sae, disp8memshift and nodefmask.
(RegZMM): New.
(Zmmword): Ditto.
(Vec_Disp8): Ditto.
(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
fields.
(RegVRex): New.
* i386-opc.tbl: Add AVX512 instructions.
* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
registers, mask registers.
* i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
|
|
|
|
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
|
|
|
|
|
|
Alexander Ivchenko <alexander.ivchenko@intel.com>
|
|
|
|
|
|
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
|
|
|
|
|
|
Sergey Lega <sergey.s.lega@intel.com>
|
|
|
|
|
|
Anna Tikhonova <anna.tikhonova@intel.com>
|
|
|
|
|
|
Ilya Tocar <ilya.tocar@intel.com>
|
|
|
|
|
|
Andrey Turetskiy <andrey.turetskiy@intel.com>
|
|
|
|
|
|
Ilya Verbin <ilya.verbin@intel.com>
|
|
|
|
|
|
Kirill Yukhin <kirill.yukhin@intel.com>
|
|
|
|
|
|
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
|
|
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|
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|
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|
|
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* config/tc-i386-intel.c (O_zmmword_ptr): New.
|
|
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|
(i386_types): Add zmmword.
|
|
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|
|
(i386_intel_simplify_register): Allow regzmm.
|
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|
|
|
(i386_intel_simplify): Handle zmmwords.
|
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(i386_intel_operand): Handle RC/SAE, vector operations and
|
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|
|
zmmwords.
|
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|
|
* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
|
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|
(struct RC_Operation): New.
|
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|
(struct Mask_Operation): New.
|
|
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|
(struct Broadcast_Operation): New.
|
|
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|
|
|
(vex_prefix): Size of bytes increased to 4 to support EVEX
|
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|
|
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encoding.
|
|
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|
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(enum i386_error): Add new error codes: unsupported_broadcast,
|
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broadcast_not_on_src_operand, broadcast_needed,
|
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unsupported_masking, mask_not_on_destination, no_default_mask,
|
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unsupported_rc_sae, rc_sae_operand_not_last_imm,
|
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invalid_register_operand, try_vector_disp8.
|
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(struct _i386_insn): Add new fields vrex, need_vrex, mask,
|
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rounding, broadcast, memshift.
|
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(struct RC_name): New.
|
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(RC_NamesTable): New.
|
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|
(evexlig): New.
|
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|
(evexwig): New.
|
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|
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(extra_symbol_chars): Add '{'.
|
|
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|
|
(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
|
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(i386_operand_type): Add regzmm, regmask and vec_disp8.
|
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(match_mem_size): Handle zmmwords.
|
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(operand_type_match): Handle zmm-registers.
|
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(mode_from_disp_size): Handle vec_disp8.
|
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(fits_in_vec_disp8): New.
|
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|
(md_begin): Handle {} properly.
|
|
|
|
|
|
(type_names): Add "rZMM", "Mask reg" and "Vector d8".
|
|
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|
|
(build_vex_prefix): Handle vrex.
|
|
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|
|
(build_evex_prefix): New.
|
|
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|
|
|
(process_immext): Adjust to properly handle EVEX.
|
|
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|
(md_assemble): Add EVEX encoding support.
|
|
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|
|
(swap_2_operands): Correctly handle operands with masking,
|
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|
broadcasting or RC/SAE.
|
|
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|
|
(check_VecOperands): Support EVEX features.
|
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|
|
|
(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
|
|
|
|
|
|
(match_template): Support regzmm and handle new error codes.
|
|
|
|
|
|
(process_suffix): Handle zmmwords and zmm-registers.
|
|
|
|
|
|
(check_byte_reg): Extend to zmm-registers.
|
|
|
|
|
|
(process_operands): Extend to zmm-registers.
|
|
|
|
|
|
(build_modrm_byte): Handle EVEX.
|
|
|
|
|
|
(output_insn): Adjust to properly handle EVEX case.
|
|
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|
|
|
(disp_size): Handle vec_disp8.
|
|
|
|
|
|
(output_disp): Support compressed disp8*N evex feature.
|
|
|
|
|
|
(output_imm): Handle RC/SAE immediates properly.
|
|
|
|
|
|
(check_VecOperations): New.
|
|
|
|
|
|
(i386_immediate): Handle EVEX features.
|
|
|
|
|
|
(i386_index_check): Handle zmmwords and zmm-registers.
|
|
|
|
|
|
(RC_SAE_immediate): New.
|
|
|
|
|
|
(i386_att_operand): Handle EVEX features.
|
|
|
|
|
|
(parse_real_register): Add a check for ZMM/Mask registers.
|
|
|
|
|
|
(OPTION_MEVEXLIG): New.
|
|
|
|
|
|
(OPTION_MEVEXWIG): New.
|
|
|
|
|
|
(md_longopts): Add mevexlig and mevexwig.
|
|
|
|
|
|
(md_parse_option): Handle mevexlig and mevexwig options.
|
|
|
|
|
|
(md_show_usage): Add description for mevexlig and mevexwig.
|
|
|
|
|
|
* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
|
|
|
|
|
|
avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
|
|
|
|
|
|
|
2013-07-26 00:16:35 +08:00
|
|
|
|
2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
|
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|
|
|
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add .sha.
|
|
|
|
|
|
* doc/c-i386.texi: Document sha/.sha.
|
|
|
|
|
|
|
2013-07-24 23:47:25 +08:00
|
|
|
|
2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
|
|
|
|
|
|
Kirill Yukhin <kirill.yukhin@intel.com>
|
|
|
|
|
|
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (BND_PREFIX): New.
|
|
|
|
|
|
(struct _i386_insn): Add new field bnd_prefix.
|
|
|
|
|
|
(add_bnd_prefix): New.
|
|
|
|
|
|
(cpu_arch): Add MPX.
|
|
|
|
|
|
(i386_operand_type): Add regbnd.
|
|
|
|
|
|
(md_assemble): Handle BND prefixes.
|
|
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|
|
(parse_insn): Likewise.
|
|
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|
|
|
(output_branch): Likewise.
|
|
|
|
|
|
(output_jump): Likewise.
|
|
|
|
|
|
(build_modrm_byte): Handle regbnd.
|
|
|
|
|
|
(OPTION_MADD_BND_PREFIX): New.
|
|
|
|
|
|
(md_longopts): Add entry for 'madd-bnd-prefix'.
|
|
|
|
|
|
(md_parse_option): Handle madd-bnd-prefix option.
|
|
|
|
|
|
(md_show_usage): Add description for madd-bnd-prefix
|
|
|
|
|
|
option.
|
|
|
|
|
|
* doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix.
|
|
|
|
|
|
|
2013-07-24 22:12:41 +08:00
|
|
|
|
2013-07-24 Tristan Gingold <gingold@adacore.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on
|
|
|
|
|
|
xcoff targets.
|
|
|
|
|
|
|
2013-07-24 17:02:45 +08:00
|
|
|
|
2013-07-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-s390.c (s390_machine): Don't force the .machine
|
|
|
|
|
|
argument to lower case.
|
|
|
|
|
|
|
2013-07-22 17:05:04 +08:00
|
|
|
|
2013-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (s_arm_arch_extension): Improve error message
|
|
|
|
|
|
for invalid extension.
|
|
|
|
|
|
|
2013-07-20 00:25:54 +08:00
|
|
|
|
2013-07-19 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag.
|
|
|
|
|
|
(AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
|
|
|
|
|
|
(aarch64_abi): New variable.
|
|
|
|
|
|
(ilp32_p): Change to be a macro.
|
|
|
|
|
|
(aarch64_opts): Remove the support for option -milp32 and -mlp64.
|
|
|
|
|
|
(struct aarch64_option_abi_value_table): New struct.
|
|
|
|
|
|
(aarch64_abis): New table.
|
|
|
|
|
|
(aarch64_parse_abi): New function.
|
|
|
|
|
|
(aarch64_long_opts): Add entry for -mabi=.
|
|
|
|
|
|
* doc/as.texinfo (Target AArch64 options): Document -mabi.
|
|
|
|
|
|
* doc/c-aarch64.texi: Likewise.
|
|
|
|
|
|
|
2013-07-19 00:12:35 +08:00
|
|
|
|
2013-07-18 Jim Thomas <thomas@cfht.hawaii.edu>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386-intel.c (i386_intel_operand): Fixed signed vs
|
|
|
|
|
|
unsigned comparison.
|
|
|
|
|
|
|
2013-07-18 20:15:15 +08:00
|
|
|
|
2013-07-18 Sandeep Kumar Singh <Sandeep.Singh2@kpitcummins.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/rx-defs.h: Add macros for RX100, RX200, RX600, and
|
|
|
|
|
|
RX610.
|
|
|
|
|
|
* config/rx-parse.y: (rx_check_float_support): Add function to
|
|
|
|
|
|
check floating point operation support for target RX100 and
|
|
|
|
|
|
RX200.
|
|
|
|
|
|
* config/tc-rx.c: Add CPU options RX100, RX200, RX600, and RX610.
|
|
|
|
|
|
* doc/c-rx.texi: Add -mcpu option to recognize macros for RX100,
|
|
|
|
|
|
RX200, RX600, and RX610
|
|
|
|
|
|
|
2013-07-18 19:52:47 +08:00
|
|
|
|
2013-07-18 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-avr.c (md_show_usage): Add avrxmega2 to help text
|
|
|
|
|
|
|
2013-07-18 19:47:30 +08:00
|
|
|
|
2013-07-18 Vishnu K.S <vishnu.k_s@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-avr.c: Make ata6289's ISA to AVR_ISA_AVR4.
|
|
|
|
|
|
* doc/c-avr.texi: Likewise.
|
|
|
|
|
|
|
2013-07-16 02:36:57 +08:00
|
|
|
|
2013-07-15 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (match_save_restore_list_operand): Avoid -Wformat
|
|
|
|
|
|
error with older GCCs.
|
|
|
|
|
|
(mips16_macro_build): Dereference args.
|
|
|
|
|
|
|
gas/
* config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register):
New functions, split out from...
(reg_lookup): ...here. Remove itbl support.
(reglist_lookup): Delete.
(mips_operand_token_type): New enum.
(mips_operand_token): New structure.
(mips_operand_tokens): New variable.
(mips_add_token, mips_parse_base_start, mips_parse_argument_token)
(mips_parse_arguments): New functions.
(md_begin): Initialize mips_operand_tokens.
(mips_arg_info): Add a token field. Remove optional_reg field.
(match_char, match_expression): New functions.
(match_const_int): Use match_expression. Remove "s" argument
and return a boolean result. Remove O_register handling.
(match_regno, match_reg, match_reg_range): New functions.
(match_int_operand, match_mapped_int_operand, match_msb_operand)
(match_reg_operand, match_reg_pair_operand, match_perf_reg_operand)
(match_addiusp_operand, match_clo_clz_dest_operand)
(match_lwm_swm_list_operand, match_entry_exit_operand)
(match_save_restore_list_operand, match_mdmx_imm_reg_operand)
(match_tied_reg_operand): Remove "s" argument and return a boolean
result. Match tokens rather than text. Update calls to
match_const_int. Rely on match_regno to call check_regno.
(match_pcrel_operand, match_pc_operand): Replace "s" argument with
"arg" argument. Return a boolean result.
(parse_float_constant): Replace with...
(match_float_constant): ...this new function.
(match_operand): Remove "s" argument and return a boolean result.
Update calls to subfunctions.
(mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines
rather than string-parsing routines. Update handling of optional
registers for token scheme.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: Add some more cases.
* gas/mips/micromips-ill.s, gas/mips/micromips-ill.l: New test.
* gas/mips/mips.exp: Run it.
2013-07-14 22:16:03 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register):
|
|
|
|
|
|
New functions, split out from...
|
|
|
|
|
|
(reg_lookup): ...here. Remove itbl support.
|
|
|
|
|
|
(reglist_lookup): Delete.
|
|
|
|
|
|
(mips_operand_token_type): New enum.
|
|
|
|
|
|
(mips_operand_token): New structure.
|
|
|
|
|
|
(mips_operand_tokens): New variable.
|
|
|
|
|
|
(mips_add_token, mips_parse_base_start, mips_parse_argument_token)
|
|
|
|
|
|
(mips_parse_arguments): New functions.
|
|
|
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|
|
(md_begin): Initialize mips_operand_tokens.
|
|
|
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|
|
(mips_arg_info): Add a token field. Remove optional_reg field.
|
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|
|
|
|
(match_char, match_expression): New functions.
|
|
|
|
|
|
(match_const_int): Use match_expression. Remove "s" argument
|
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|
|
|
|
and return a boolean result. Remove O_register handling.
|
|
|
|
|
|
(match_regno, match_reg, match_reg_range): New functions.
|
|
|
|
|
|
(match_int_operand, match_mapped_int_operand, match_msb_operand)
|
|
|
|
|
|
(match_reg_operand, match_reg_pair_operand, match_perf_reg_operand)
|
|
|
|
|
|
(match_addiusp_operand, match_clo_clz_dest_operand)
|
|
|
|
|
|
(match_lwm_swm_list_operand, match_entry_exit_operand)
|
|
|
|
|
|
(match_save_restore_list_operand, match_mdmx_imm_reg_operand)
|
|
|
|
|
|
(match_tied_reg_operand): Remove "s" argument and return a boolean
|
|
|
|
|
|
result. Match tokens rather than text. Update calls to
|
|
|
|
|
|
match_const_int. Rely on match_regno to call check_regno.
|
|
|
|
|
|
(match_pcrel_operand, match_pc_operand): Replace "s" argument with
|
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|
|
|
"arg" argument. Return a boolean result.
|
|
|
|
|
|
(parse_float_constant): Replace with...
|
|
|
|
|
|
(match_float_constant): ...this new function.
|
|
|
|
|
|
(match_operand): Remove "s" argument and return a boolean result.
|
|
|
|
|
|
Update calls to subfunctions.
|
|
|
|
|
|
(mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines
|
|
|
|
|
|
rather than string-parsing routines. Update handling of optional
|
|
|
|
|
|
registers for token scheme.
|
|
|
|
|
|
|
2013-07-14 21:53:47 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (parse_float_constant): Split out from...
|
|
|
|
|
|
(mips_ip): ...here.
|
|
|
|
|
|
|
2013-07-14 21:52:52 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (INSERT_BITS, INSERT_OPERAND, MIPS16_INSERT_OPERAND):
|
|
|
|
|
|
Delete.
|
|
|
|
|
|
|
2013-07-14 21:51:52 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips32_to_16_reg_map): Delete.
|
|
|
|
|
|
(match_entry_exit_operand): New function.
|
|
|
|
|
|
(match_save_restore_list_operand): Likewise.
|
|
|
|
|
|
(match_operand): Use them.
|
|
|
|
|
|
(check_absolute_expr): Delete.
|
|
|
|
|
|
(mips16_ip): Rewrite main parsing loop to use mips_operands.
|
|
|
|
|
|
|
gas/
* config/tc-mips.c: Enable functions commented out in previous patch.
(SKIP_SPACE_TABS): Move further up file.
(mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map)
(mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map)
(ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map)
(mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map)
(mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map)
(micromips_imm_b_map, micromips_imm_c_map): Delete.
(mips_lookup_reg_pair): Delete.
(macro): Use report_bad_range and report_bad_field.
(mips_immed, expr_const_in_range): Delete.
(mips_ip): Rewrite main parsing loop to use new functions.
gas/testsuite/
* gas/mips/at-2.l: Remove duplicated $at warnings.
* gas/mips/ext-ill.l, gas/mips/lui-1.l, gas/mips/mips32r2-ill.l,
gas/mips/mips32r2-ill-nofp.l, gas/mips/mips32r2-ill-fp64.l,
gas/mips/mips64r2-ill.l, gas/mips/octeon-ill.l: Update error
messages. Expect negative numbers to be printed as such,
rather than as large unsigned positive numbers.
2013-07-14 21:49:14 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c: Enable functions commented out in previous patch.
|
|
|
|
|
|
(SKIP_SPACE_TABS): Move further up file.
|
|
|
|
|
|
(mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map)
|
|
|
|
|
|
(mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map)
|
|
|
|
|
|
(ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map)
|
|
|
|
|
|
(mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map)
|
|
|
|
|
|
(mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map)
|
|
|
|
|
|
(micromips_imm_b_map, micromips_imm_c_map): Delete.
|
|
|
|
|
|
(mips_lookup_reg_pair): Delete.
|
|
|
|
|
|
(macro): Use report_bad_range and report_bad_field.
|
|
|
|
|
|
(mips_immed, expr_const_in_range): Delete.
|
|
|
|
|
|
(mips_ip): Rewrite main parsing loop to use new functions.
|
|
|
|
|
|
|
gas/
* config/tc-mips.c (mips_oddfpreg_ok): Move further up file.
Change return type to bfd_boolean.
(report_bad_range, report_bad_field): New functions.
(mips_arg_info): New structure.
(match_const_int, convert_reg_type, check_regno, match_int_operand)
(match_mapped_int_operand, match_msb_operand, match_reg_operand)
(match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand)
(match_addiusp_operand, match_clo_clz_dest_operand)
(match_lwm_swm_list_operand, match_mdmx_imm_reg_operand)
(match_pc_operand, match_tied_reg_operand, match_operand)
(check_completed_insn): New functions, commented out for now.
2013-07-14 21:44:25 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_oddfpreg_ok): Move further up file.
|
|
|
|
|
|
Change return type to bfd_boolean.
|
|
|
|
|
|
(report_bad_range, report_bad_field): New functions.
|
|
|
|
|
|
(mips_arg_info): New structure.
|
|
|
|
|
|
(match_const_int, convert_reg_type, check_regno, match_int_operand)
|
|
|
|
|
|
(match_mapped_int_operand, match_msb_operand, match_reg_operand)
|
|
|
|
|
|
(match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand)
|
|
|
|
|
|
(match_addiusp_operand, match_clo_clz_dest_operand)
|
|
|
|
|
|
(match_lwm_swm_list_operand, match_mdmx_imm_reg_operand)
|
|
|
|
|
|
(match_pc_operand, match_tied_reg_operand, match_operand)
|
|
|
|
|
|
(check_completed_insn): New functions, commented out for now.
|
|
|
|
|
|
|
2013-07-14 21:37:51 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (insn_insert_operand): New function.
|
|
|
|
|
|
(macro_build, mips16_macro_build): Put null character check
|
|
|
|
|
|
in the for loop and convert continues to breaks. Use operand
|
|
|
|
|
|
structures to handle constant operands.
|
|
|
|
|
|
|
include/opcode/
* mips.h (mips_operand_type, mips_reg_operand_type): New enums.
(mips_operand, mips_int_operand, mips_mapped_int_operand)
(mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
(mips_pcrel_operand): New structures.
(mips_insert_operand, mips_extract_operand, mips_signed_operand)
(mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
(decode_mips_operand, decode_micromips_operand): Declare.
opcodes/
* mips-formats.h: New file.
* mips-opc.c: Include mips-formats.h.
(reg_0_map): New static array.
(decode_mips_operand): New function.
* micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
(reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
(reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
(int_c_map): New static arrays.
(decode_micromips_operand): New function.
* mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
(micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
(micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
(micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
(micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
(micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
(micromips_imm_b_map, micromips_imm_c_map): Delete.
(print_reg): New function.
(mips_print_arg_state): New structure.
(init_print_arg_state, print_insn_arg): New functions.
(print_insn_args): Change interface and use mips_operand structures.
Delete GET_OP_S. Move GET_OP definition to...
(print_insn_mips): ...here. Update the call to print_insn_args.
(print_insn_micromips): Use print_insn_args.
gas/
* config/tc-mips.c (validate_mips_insn): Move further up file.
Add insn_bits and decode_operand arguments. Use the mips_operand
fields to work out which bits an operand occupies. Detect double
definitions.
(validate_micromips_insn): Move further up file. Call into
validate_mips_insn.
2013-07-14 21:28:56 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (validate_mips_insn): Move further up file.
|
|
|
|
|
|
Add insn_bits and decode_operand arguments. Use the mips_operand
|
|
|
|
|
|
fields to work out which bits an operand occupies. Detect double
|
|
|
|
|
|
definitions.
|
|
|
|
|
|
(validate_micromips_insn): Move further up file. Call into
|
|
|
|
|
|
validate_mips_insn.
|
|
|
|
|
|
|
2013-07-14 21:17:55 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips16_macro_build): Remove 'Y' case.
|
|
|
|
|
|
|
2013-07-14 21:15:25 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (macro_build): Take an int for "C", "k", "\\"
|
|
|
|
|
|
and "~".
|
|
|
|
|
|
(macro): Update accordingly.
|
|
|
|
|
|
|
2013-07-14 21:13:43 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (imm_expr, imm2_expr, offset_expr): Tweak commentary.
|
|
|
|
|
|
(imm_reloc): Delete.
|
|
|
|
|
|
(md_assemble): Remove imm_reloc handling.
|
|
|
|
|
|
(mips_ip): Update commentary. Use offset_expr and offset_reloc
|
|
|
|
|
|
rather than imm_expr and imm_reloc for 'i', 'j' and 'u'.
|
|
|
|
|
|
Use a temporary array rather than imm_reloc when parsing
|
|
|
|
|
|
constant expressions. Remove imm_reloc initialization.
|
|
|
|
|
|
(mips16_ip): Update commentary. Use offset_expr and offset_reloc
|
|
|
|
|
|
for the relaxable field. Use a relax_char variable to track the
|
|
|
|
|
|
type of this field. Remove imm_reloc initialization.
|
|
|
|
|
|
|
2013-07-14 21:11:03 +08:00
|
|
|
|
2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips16_ip): Handle "I".
|
|
|
|
|
|
|
2013-07-12 23:58:15 +08:00
|
|
|
|
2013-07-12 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_flag_nan2008): New variable.
|
|
|
|
|
|
(options): Add OPTION_NAN enum value.
|
|
|
|
|
|
(md_longopts): Handle it.
|
|
|
|
|
|
(md_parse_option): Likewise.
|
|
|
|
|
|
(s_nan): New function.
|
|
|
|
|
|
(mips_elf_final_processing): Handle EF_MIPS_NAN2008.
|
|
|
|
|
|
(md_show_usage): Add -mnan.
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (Overview): Add -mnan.
|
|
|
|
|
|
* doc/c-mips.texi (MIPS Opts): Document -mnan.
|
|
|
|
|
|
(MIPS NaN Encodings): New node. Document .nan directive.
|
|
|
|
|
|
(MIPS-Dependent): List the new node.
|
|
|
|
|
|
|
2013-07-09 15:32:14 +08:00
|
|
|
|
2013-07-09 Tristan Gingold <gingold@adacore.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H
|
|
|
|
|
|
|
2013-07-08 16:39:32 +08:00
|
|
|
|
2013-07-08 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_ip): Unconditionally parse an expression
|
|
|
|
|
|
for 'A' and assume that the constant has been elided if the result
|
|
|
|
|
|
is an O_register.
|
|
|
|
|
|
|
include/opcode/
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
Rename to...
(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
(M_USD_AB): ...these.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
and SD A(B) macros up.
* micromips-opc.c (micromips_opcodes): Likewise.
gas/
* config/tc-mips.c (gprel16_reloc_p): New function.
(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
BFD_RELOC_UNUSED.
(offset_high_part, small_offset_p): New functions.
(nacro): Use them. Remove *_OB and *_DOB cases. For single-
register load and store macros, handle the 16-bit offset case first.
If a 16-bit offset is not suitable for the instruction we're
generating, load it into the temporary register using
ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
M_L_DAB code once the address has been constructed. For double load
and store macros, again handle the 16-bit offset case first.
If the second register cannot be accessed from the same high
part as the first, load it into AT using ADDRESS_ADDI_INSN.
Fix the handling of LD in cases where the first register is the
same as the base. Also handle the case where the offset is
not 16 bits and the second register cannot be accessed from the
same high part as the first. For unaligned loads and stores,
fuse the offbits == 12 and old "ab" handling. Apply this handling
whenever the second offset needs a different high part from the first.
Construct the offset using ADDRESS_ADDI_INSN where possible,
for offbits == 16 as well as offbits == 12. Use offset_reloc
when constructing the individual loads and stores.
(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
and offset_reloc before matching against a particular opcode.
Handle elided 'A' constants. Allow 'A' constants to use
relocation operators.
gas/testsuite/
* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
truncated constants.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
16-bit constants to the base.
* gas/mips/micromips@mcu.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
Allow the full 16-bit offset range to be used for SB, LB and LBU in
USH and ULH sequences. Fix the expected output for LD and SD when
the two LW and SW offsets need different high parts.
* gas/mips/eva.s: Test PREFE with relocation operators.
* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
constants. Update after eva.s change.
* gas/mips/micromips@eva.d: Likewise.
* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
gas/mips/ulh-reloc.d: New tests.
* gas/mips/mips.exp: Run them.
2013-07-07 19:32:32 +08:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (gprel16_reloc_p): New function.
|
|
|
|
|
|
(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
|
|
|
|
|
|
BFD_RELOC_UNUSED.
|
|
|
|
|
|
(offset_high_part, small_offset_p): New functions.
|
|
|
|
|
|
(nacro): Use them. Remove *_OB and *_DOB cases. For single-
|
|
|
|
|
|
register load and store macros, handle the 16-bit offset case first.
|
|
|
|
|
|
If a 16-bit offset is not suitable for the instruction we're
|
|
|
|
|
|
generating, load it into the temporary register using
|
|
|
|
|
|
ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
|
|
|
|
|
|
M_L_DAB code once the address has been constructed. For double load
|
|
|
|
|
|
and store macros, again handle the 16-bit offset case first.
|
|
|
|
|
|
If the second register cannot be accessed from the same high
|
|
|
|
|
|
part as the first, load it into AT using ADDRESS_ADDI_INSN.
|
|
|
|
|
|
Fix the handling of LD in cases where the first register is the
|
|
|
|
|
|
same as the base. Also handle the case where the offset is
|
|
|
|
|
|
not 16 bits and the second register cannot be accessed from the
|
|
|
|
|
|
same high part as the first. For unaligned loads and stores,
|
|
|
|
|
|
fuse the offbits == 12 and old "ab" handling. Apply this handling
|
|
|
|
|
|
whenever the second offset needs a different high part from the first.
|
|
|
|
|
|
Construct the offset using ADDRESS_ADDI_INSN where possible,
|
|
|
|
|
|
for offbits == 16 as well as offbits == 12. Use offset_reloc
|
|
|
|
|
|
when constructing the individual loads and stores.
|
|
|
|
|
|
(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
|
|
|
|
|
|
and offset_reloc before matching against a particular opcode.
|
|
|
|
|
|
Handle elided 'A' constants. Allow 'A' constants to use
|
|
|
|
|
|
relocation operators.
|
|
|
|
|
|
|
2013-07-07 18:15:09 +08:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
|
|
|
|
|
|
(mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
|
|
|
|
|
|
Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
|
|
|
|
|
|
|
2013-07-07 18:00:43 +08:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
|
|
|
|
|
|
Require the msb to be <= 31 for "+s". Check that the size is <= 31
|
|
|
|
|
|
for both "+s" and "+S".
|
|
|
|
|
|
|
2013-07-07 17:50:43 +08:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
|
|
|
|
|
|
(mips_ip, mips16_ip): Handle "+i".
|
|
|
|
|
|
|
2013-07-07 17:41:04 +08:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
|
|
|
|
|
|
(micromips_to_32_reg_h_map): Rename to...
|
|
|
|
|
|
(micromips_to_32_reg_h_map1): ...this.
|
|
|
|
|
|
(micromips_to_32_reg_i_map): Rename to...
|
|
|
|
|
|
(micromips_to_32_reg_h_map2): ...this.
|
|
|
|
|
|
(mips_lookup_reg_pair): New function.
|
|
|
|
|
|
(gpr_write_mask, macro): Adjust after above renaming.
|
|
|
|
|
|
(validate_micromips_insn): Remove "mi" handling.
|
|
|
|
|
|
(mips_ip): Likewise. Parse both registers in a pair for "mh".
|
|
|
|
|
|
|
2013-07-07 17:32:55 +08:00
|
|
|
|
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
|
|
|
|
|
|
(mips_ip): Remove "+D" and "+T" handling.
|
|
|
|
|
|
|
2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
opcodes/
* s390-opc.c (J12_12, J24_24): New macros.
(INSTR_MII_UPI): Rename to INSTR_MII_UPP.
(MASK_MII_UPI): Rename to MASK_MII_UPP.
* s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
include/elf/
* s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL,
R_390_PC24DBL, and R_390_PLT24DBL.
gas/testsuite/
* gas/s390/zarch-zEC12.s: Change bprp second operand and add
variants requiring relocations.
* gas/s390/zarch-zEC12.d: Likewise.
gas/
* config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
relocs.
bfd/
* elf32-s390.c: Add new relocation definitions R_390_PC12DBL,
R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL.
(elf_s390_reloc_type_lookup, elf_s390_check_relocs)
(elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new
relocations.
* elf64-s390.c: See elf32-s390.c
* bfd-in2.h: Add new relocs to enum bfd_reloc_code_real.
* libbfd.h: Add new reloc strings.
2013-07-05 17:45:44 +08:00
|
|
|
|
2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
|
|
|
|
|
|
relocs.
|
|
|
|
|
|
|
2013-07-04 01:25:17 +08:00
|
|
|
|
2013-07-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
|
|
|
|
|
|
|
2013-07-04 01:26:36 +08:00
|
|
|
|
* config/tc-aarch64.c (reloc_table): Merge got_prel19 into got.
|
|
|
|
|
|
|
|
|
|
|
|
2013-07-02 Marcus Shawcroft <marcus.shawcroft@arm.com>
|
|
|
|
|
|
|
2013-07-04 01:25:17 +08:00
|
|
|
|
* config/tc-aarch64.c (md_apply_fix): Reorder case values.
|
|
|
|
|
|
(aarch64_force_relocation): Likewise.
|
|
|
|
|
|
|
2013-07-02 08:25:08 +08:00
|
|
|
|
2013-07-02 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak.
|
|
|
|
|
|
|
2013-06-26 20:15:43 +08:00
|
|
|
|
2013-06-26 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
|
|
|
|
|
|
* doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
|
|
|
|
|
|
Replace @sc{mips16} with literal `MIPS16'.
|
|
|
|
|
|
(MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
|
|
|
|
|
|
|
2013-06-26 18:47:06 +08:00
|
|
|
|
2013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (reloc_table): Replace
|
|
|
|
|
|
BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with
|
|
|
|
|
|
BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC.
|
|
|
|
|
|
(md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
|
|
|
|
|
|
BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and
|
|
|
|
|
|
BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC.
|
|
|
|
|
|
(aarch64_force_relocation): Likewise.
|
|
|
|
|
|
|
2013-06-26 18:41:42 +08:00
|
|
|
|
2013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (ilp32_p): New static variable.
|
|
|
|
|
|
(elf64_aarch64_target_format): Return the target according to the
|
|
|
|
|
|
value of 'ilp32_p'.
|
|
|
|
|
|
(md_begin): Determine 'mach' according to the value of 'ilp32_p'.
|
|
|
|
|
|
(aarch64_opts): Add support for options '-milp32' and '-mlp64'.
|
|
|
|
|
|
(aarch64_dwarf2_addr_size): New function.
|
|
|
|
|
|
* config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
|
|
|
|
|
|
(DWARF2_ADDR_SIZE): New define.
|
|
|
|
|
|
|
2013-06-26 16:04:00 +08:00
|
|
|
|
2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-mips.texi: Use ISA instead of @sc{isa}.
|
|
|
|
|
|
|
2013-06-26 15:04:57 +08:00
|
|
|
|
2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
|
|
|
|
|
|
|
bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype.
* elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member.
(STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros.
(MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise.
(MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise.
(micromips_insn32_o32_exec_plt0_entry): New variable.
(micromips_insn32_o32_exec_plt_entry): Likewise.
(_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode.
(mips_elf_estimate_stub_size): Likewise.
(_bfd_mips_elf_size_dynamic_sections): Likewise.
(_bfd_mips_elf_finish_dynamic_symbol): Likewise.
(mips_finish_exec_plt): Likewise.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips_elf_insn32): New function.
(_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT.
gas/
* config/tc-mips.c (mips_set_options): Add insn32 member.
(mips_opts): Initialize it.
(NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
(options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
(md_longopts): Add "minsn32" and "mno-insn32" options.
(is_size_valid): Handle insn32 mode.
(md_assemble): Pass instruction string down to macro.
(brk_fmt): Add second dimension and insn32 mode initializers.
(mfhl_fmt): Likewise.
(BRK_FMT, MFHL_FMT): Handle insn32 mode.
(macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
(macro_build_jalr, move_register): Handle insn32 mode.
(macro_build_branch_rs): Likewise.
(macro): Handle insn32 mode.
<M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
(mips_ip): Handle insn32 mode.
(md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
(s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
(mips_handle_align): Handle insn32 mode.
(md_show_usage): Add -minsn32 and -mno-insn32.
* doc/as.texinfo (Target MIPS options): Add -minsn32 and
-mno-insn32 options.
(-minsn32, -mno-insn32): New options.
* doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
options.
(MIPS assembly options): New node. Document .set insn32 and
.set noinsn32.
(MIPS-Dependent): List the new node.
gas/testsuite/
* gas/mips/micromips-insn32.d: New test.
* gas/mips/micromips-noinsn32.d: Likewise.
* gas/mips/micromips.l: Rename to...
* gas/mips/micromips-warn.l: ... this.
* gas/mips/micromips.d: Update accordingly.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New list test.
* gas/mips/micromips.s: Add conditionals.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
values.
ld/
* emultempl/mipself.em (insn32): New variable.
(mips_create_output_section_statements): Handle insn32 mode.
(PARSE_AND_LIST_PROLOGUE): New macro.
(PARSE_AND_LIST_LONGOPTS): Likewise.
(PARSE_AND_LIST_OPTIONS): Likewise.
* gen-doc.texi: Set MIPS.
* ld.texinfo: Likewise.
(Options specific to MIPS targets): New section.
(ld and MIPS family): New node.
(Top, Machine Dependent): List the new node.
opcodes/
* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
and "movep" macros.
2013-06-26 02:02:34 +08:00
|
|
|
|
2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_set_options): Add insn32 member.
|
|
|
|
|
|
(mips_opts): Initialize it.
|
|
|
|
|
|
(NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
|
|
|
|
|
|
(options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
|
|
|
|
|
|
(md_longopts): Add "minsn32" and "mno-insn32" options.
|
|
|
|
|
|
(is_size_valid): Handle insn32 mode.
|
|
|
|
|
|
(md_assemble): Pass instruction string down to macro.
|
|
|
|
|
|
(brk_fmt): Add second dimension and insn32 mode initializers.
|
|
|
|
|
|
(mfhl_fmt): Likewise.
|
|
|
|
|
|
(BRK_FMT, MFHL_FMT): Handle insn32 mode.
|
|
|
|
|
|
(macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
|
|
|
|
|
|
(macro_build_jalr, move_register): Handle insn32 mode.
|
|
|
|
|
|
(macro_build_branch_rs): Likewise.
|
|
|
|
|
|
(macro): Handle insn32 mode.
|
|
|
|
|
|
<M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
|
|
|
|
|
|
(mips_ip): Handle insn32 mode.
|
|
|
|
|
|
(md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
|
|
|
|
|
|
(s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
|
|
|
|
|
|
(mips_handle_align): Handle insn32 mode.
|
|
|
|
|
|
(md_show_usage): Add -minsn32 and -mno-insn32.
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo (Target MIPS options): Add -minsn32 and
|
|
|
|
|
|
-mno-insn32 options.
|
|
|
|
|
|
(-minsn32, -mno-insn32): New options.
|
|
|
|
|
|
* doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
|
|
|
|
|
|
options.
|
|
|
|
|
|
(MIPS assembly options): New node. Document .set insn32 and
|
|
|
|
|
|
.set noinsn32.
|
|
|
|
|
|
(MIPS-Dependent): List the new node.
|
|
|
|
|
|
|
2013-06-25 16:21:43 +08:00
|
|
|
|
2013-06-25 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-msp430.c (msp430_srcoperand): Do not allow the use of
|
|
|
|
|
|
the PC in indirect addressing on 430xv2 parts.
|
|
|
|
|
|
(msp430_operands): Add version test to hardware bug encoding
|
|
|
|
|
|
restrictions.
|
|
|
|
|
|
|
2013-06-25 05:05:30 +08:00
|
|
|
|
2013-06-24 Roland McGrath <mcgrathr@google.com>
|
|
|
|
|
|
|
2013-06-25 07:13:00 +08:00
|
|
|
|
* config/tc-arm.c (parse_reg_list): Use skip_past_char for '}',
|
|
|
|
|
|
so it skips whitespace before it.
|
|
|
|
|
|
(s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise.
|
|
|
|
|
|
|
2013-06-25 05:05:30 +08:00
|
|
|
|
* config/tc-arm.c (arm_symbol_chars): Include '{' and '}'.
|
|
|
|
|
|
(arm_reg_parse_multi): Skip whitespace first.
|
|
|
|
|
|
(parse_reg_list): Likewise.
|
|
|
|
|
|
(parse_vfp_reg_list): Likewise.
|
|
|
|
|
|
(s_arm_unwind_save_mmxwcg): Likewise.
|
|
|
|
|
|
|
2013-06-24 23:38:53 +08:00
|
|
|
|
2013-06-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15623
|
|
|
|
|
|
* config/tc-arm.c (do_t_smc): Mark as ending an IT block.
|
|
|
|
|
|
|
2013-06-24 04:12:53 +08:00
|
|
|
|
2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
|
|
|
|
|
|
|
2013-06-24 04:08:23 +08:00
|
|
|
|
2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c: Assert that offsetT and valueT are at least
|
|
|
|
|
|
8 bytes in size.
|
|
|
|
|
|
(GPR_SMIN, GPR_SMAX): New macros.
|
|
|
|
|
|
(macro, mips_ip): Remove code for 4-byte valueT and offsetT.
|
|
|
|
|
|
|
2013-06-23 00:49:08 +08:00
|
|
|
|
2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF
|
|
|
|
|
|
conditions. Remove any code deselected by them.
|
|
|
|
|
|
(s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first.
|
|
|
|
|
|
|
* configure.ac (mips*-*-bsd*, mips*-*-ultrix*, mips*-*-osf*)
(mips*-*-ecoff*, mips*-*-pe*, mips*-*-irix* [v4 and earlier])
(mips*-*-lnews*, mips*-*-riscos*): Add gas and ld to noconfigdirs.
* configure: Regenerate.
gas/
* NEWS: Note removal of ECOFF support.
* doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF.
* Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h.
(MULTI_CFILES): Remove config/e-mipsecoff.c.
* Makefile.in: Regenerate.
* configure.in: Remove MIPS ECOFF references.
(mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff):
Delete cases.
(mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*)
(mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into...
(mips-*-*): ...this single case.
(mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect
MIPS emulations to be e-mipself*.
* configure: Regenerate.
* configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*)
(mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*)
(mips-*-sysv*): Remove coff and ecoff cases.
* as.c (mipsbecoff, mipslecoff, mipsecoff): Remove.
* ecoff.c: Remove reference to MIPS ECOFF.
* config/e-mipsecoff.c, config/te-lnews.h: Delete files.
* config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete.
(RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases.
(mips_hi_fixup): Tweak comment.
(append_insn): Require a howto.
(mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code.
gas/testsuite/
* gas/all/gas.exp: Remove reference to mips-ecoff.
* gas/mips/branch-misc-1.d, gas/mips/branch-misc-2.d,
gas/mips/branch-misc-2-64.d, gas/mips/branch-misc-2pic.d,
gas/mips/branch-misc-2pic-64.d, gas/mips/branch-swap.d: Remove
skips for mips-*-ecoff.
ld/
* NEWS: Document the removal of MIPS ECOFF targets.
* ld.texinfo (--gpsize=@var{value}): Use MIPS ELF rather than
MIPS ECOFF as an example of a target that supports small data.
* ldmain.c (g_switch_value): Likewise.
* configure.tgt (mips*-*-pe, mips*-dec-ultrix*, mips*-dec-osf*)
(mips*-sgi-irix* [v4 and earlier], mips*el-*-ecoff*, mips*-*-ecoff*)
(mips*-*-bsd*, mips*-*-lnews*): Remove cases.
* Makefile.am (ALL_EMULATION_SOURCES): Remove emipsbig.c, emipsbsd.c,
emipsidt.c, emipsidtl.c, emipslit.c, emipslnews.c and emipspe.c.
(emipsbig.c, emipsbsd.c, emipsidt.c, emipsidtl.c, emipslit.c)
(emipslnews.c, emipspe.c): Delete rules.
* Makefile.in: Regenerate.
* emulparams/mipsbig.sh, emulparams/mipsbsd.sh, emulparams/mipsidt.sh,
emulparams/mipsidtl.sh, emulparams/mipslit.sh, emulparams/mipslnews.sh,
emulparams/mipspe.sh, emultempl/mipsecoff.em: Delete.
* emultempl/m68kcoff.em: Update comment to say that MIPS ECOFF support
has now been removed.
* emultempl/pe.em: Remove TARGET_IS_mipspe checks.
2013-06-23 00:44:16 +08:00
|
|
|
|
2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* NEWS: Note removal of ECOFF support.
|
|
|
|
|
|
* doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF.
|
|
|
|
|
|
* Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h.
|
|
|
|
|
|
(MULTI_CFILES): Remove config/e-mipsecoff.c.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure.in: Remove MIPS ECOFF references.
|
|
|
|
|
|
(mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff):
|
|
|
|
|
|
Delete cases.
|
|
|
|
|
|
(mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*)
|
|
|
|
|
|
(mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into...
|
|
|
|
|
|
(mips-*-*): ...this single case.
|
|
|
|
|
|
(mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect
|
|
|
|
|
|
MIPS emulations to be e-mipself*.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*)
|
|
|
|
|
|
(mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*)
|
|
|
|
|
|
(mips-*-sysv*): Remove coff and ecoff cases.
|
|
|
|
|
|
* as.c (mipsbecoff, mipslecoff, mipsecoff): Remove.
|
|
|
|
|
|
* ecoff.c: Remove reference to MIPS ECOFF.
|
|
|
|
|
|
* config/e-mipsecoff.c, config/te-lnews.h: Delete files.
|
|
|
|
|
|
* config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete.
|
|
|
|
|
|
(RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases.
|
|
|
|
|
|
(mips_hi_fixup): Tweak comment.
|
|
|
|
|
|
(append_insn): Require a howto.
|
|
|
|
|
|
(mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code.
|
|
|
|
|
|
|
2013-06-23 00:18:45 +08:00
|
|
|
|
2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
|
|
|
|
|
|
Use "CPU" instead of "cpu".
|
|
|
|
|
|
* doc/c-mips.texi: Likewise.
|
|
|
|
|
|
(MIPS Opts): Rename to MIPS Options.
|
|
|
|
|
|
(MIPS option stack): Rename to MIPS Option Stack.
|
|
|
|
|
|
(MIPS ASE instruction generation overrides): Rename to
|
|
|
|
|
|
MIPS ASE Instruction Generation Overrides (for now).
|
|
|
|
|
|
(MIPS floating-point): Rename to MIPS Floating-Point.
|
|
|
|
|
|
|
2013-06-23 00:09:55 +08:00
|
|
|
|
2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-mips.texi (MIPS Macros): New section.
|
|
|
|
|
|
(MIPS Object): Replace with...
|
|
|
|
|
|
(MIPS Small Data): ...this new section.
|
|
|
|
|
|
|
2013-06-23 00:02:24 +08:00
|
|
|
|
2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-mips.texi (MIPS symbol sizes): Move section further up file.
|
|
|
|
|
|
Capitalize name. Use @kindex instead of @cindex for .set entries.
|
|
|
|
|
|
|
2013-06-22 23:58:59 +08:00
|
|
|
|
2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-mips.texi (MIPS Stabs): Remove section.
|
|
|
|
|
|
|
gas/
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
(ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
(ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
(ISA_SUPPORTS_VIRT64_ASE): Delete.
(mips_ase): New structure.
(mips_ases): New table.
(FP64_ASES): New macro.
(mips_ase_groups): New array.
(mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
(mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
functions.
(is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
(md_parse_option): Use mips_ases and mips_set_ase instead of
separate case statements for each ASE option.
(mips_after_parse_args): Use FP64_ASES. Use
mips_check_isa_supports_ases to check the ASEs against
other options.
(s_mipsset): Use mips_ases and mips_set_ase instead of
separate if statements for each ASE option. Use
mips_check_isa_supports_ases, even when a non-ASE option
is specified.
gas/testsuite/
* gas/mips/ase-errors-1.s, gas/mips/ase-errors-1.l,
gas/mips/ase-errors-2.s, gas/mips/ase-errors-2.l,
gas/mips/ase-errors-3.s, gas/mips/ase-errors-3.l,
gas/mips/ase-errors-4.s, gas/mips/ase-errors-4.l: New tests.
* gas/mips/mips.exp: Run them.
2013-06-21 03:25:20 +08:00
|
|
|
|
2013-06-20 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
|
|
|
|
|
|
(ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
|
|
|
|
|
|
(ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
|
|
|
|
|
|
(ISA_SUPPORTS_VIRT64_ASE): Delete.
|
|
|
|
|
|
(mips_ase): New structure.
|
|
|
|
|
|
(mips_ases): New table.
|
|
|
|
|
|
(FP64_ASES): New macro.
|
|
|
|
|
|
(mips_ase_groups): New array.
|
|
|
|
|
|
(mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
|
|
|
|
|
|
(mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
|
|
|
|
|
|
functions.
|
|
|
|
|
|
(is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
|
|
|
|
|
|
(md_parse_option): Use mips_ases and mips_set_ase instead of
|
|
|
|
|
|
separate case statements for each ASE option.
|
|
|
|
|
|
(mips_after_parse_args): Use FP64_ASES. Use
|
|
|
|
|
|
mips_check_isa_supports_ases to check the ASEs against
|
|
|
|
|
|
other options.
|
|
|
|
|
|
(s_mipsset): Use mips_ases and mips_set_ase instead of
|
|
|
|
|
|
separate if statements for each ASE option. Use
|
|
|
|
|
|
mips_check_isa_supports_ases, even when a non-ASE option
|
|
|
|
|
|
is specified.
|
|
|
|
|
|
|
2013-06-19 21:26:04 +08:00
|
|
|
|
2013-06-19 Greta Yorsh <Greta.Yorsh@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_cpus): Add support for Cortex-A12.
|
|
|
|
|
|
|
2013-06-19 03:38:48 +08:00
|
|
|
|
2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_shortopts, options, md_longopts)
|
|
|
|
|
|
(md_longopts_size): Move earlier in file.
|
|
|
|
|
|
|
2013-06-19 03:37:21 +08:00
|
|
|
|
2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields
|
|
|
|
|
|
with a single "ase" bitmask.
|
|
|
|
|
|
(mips_opts): Update accordingly.
|
|
|
|
|
|
(file_ase, file_ase_explicit): New variables.
|
|
|
|
|
|
(file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp)
|
|
|
|
|
|
(file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete.
|
|
|
|
|
|
(ISA_HAS_ROR): Adjust for mips_set_options change.
|
|
|
|
|
|
(is_opcode_valid): Take the base ase mask directly from mips_opts.
|
|
|
|
|
|
(mips_ip): Adjust for mips_set_options change.
|
|
|
|
|
|
(md_parse_option): Likewise. Update file_ase_explicit.
|
|
|
|
|
|
(mips_after_parse_args): Adjust for mips_set_options change.
|
|
|
|
|
|
Use bitmask operations to select the default ASEs. Set file_ase
|
|
|
|
|
|
rather than individual per-ASE variables.
|
|
|
|
|
|
(s_mipsset): Adjust for mips_set_options change.
|
|
|
|
|
|
(mips_elf_final_processing): Test file_ase rather than
|
|
|
|
|
|
file_ase_mdmx. Remove commented-out code.
|
|
|
|
|
|
|
2013-06-19 03:34:17 +08:00
|
|
|
|
2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_cpu_info): Add an "ase" field.
|
|
|
|
|
|
(MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
|
|
|
|
|
|
(MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
|
|
|
|
|
|
(MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
|
|
|
|
|
|
(mips_after_parse_args): Use the new "ase" field to choose
|
|
|
|
|
|
the default ASEs.
|
|
|
|
|
|
(mips_cpu_info_table): Move ASEs from the "flags" field to the
|
|
|
|
|
|
"ase" field.
|
|
|
|
|
|
|
2013-06-18 22:41:09 +08:00
|
|
|
|
2013-06-18 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (symbol_preemptible): New function.
|
|
|
|
|
|
(relax_branch): Use it.
|
|
|
|
|
|
|
2013-06-17 Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
Chao-Ying Fu <fu@mips.com>
gas/testsuite/
* gas/mips/mips.exp: Run new tests.
* gas/mips/eva.d: New.
* gas/mips/eva.s: New.
* gas/mips/micromips@eva.d: New.
gas/
* config/tc-mips.c (mips_set_options): Add ase_eva.
(mips_set_options mips_opts): Add ase_eva.
(file_ase_eva): Declare.
(ISA_SUPPORTS_EVA_ASE): Define.
(IS_SEXT_9BIT_NUM): Define.
(MIPS_CPU_ASE_EVA): Define.
(is_opcode_valid): Add support for ase_eva.
(macro_build): Likewise.
(macro): Likewise.
(validate_mips_insn): Likewise.
(validate_micromips_insn): Likewise.
(mips_ip): Likewise.
(options): Add OPTION_EVA and OPTION_NO_EVA.
(md_longopts): Add -meva and -mno-eva.
(md_parse_option): Process new options.
(mips_after_parse_args): Check for valid EVA combinations.
(s_mipsset): Likewise.
include/
* opcode/mips.h (OP_SH_EVAOFFSET): Define.
(OP_MASK_EVAOFFSET): Define.
(INSN_ASE_MASK): Delete.
(ASE_EVA): Define.
(M_CACHEE_AB, M_CACHEE_OB): New.
(M_LBE_OB, M_LBE_AB): New.
(M_LBUE_OB, M_LBUE_AB): New.
(M_LHE_OB, M_LHE_AB): New.
(M_LHUE_OB, M_LHUE_AB): New.
(M_LLE_AB, M_LLE_OB): New.
(M_LWE_OB, M_LWE_AB): New.
(M_LWLE_AB, M_LWLE_OB): New.
(M_LWRE_AB, M_LWRE_OB): New.
(M_PREFE_AB, M_PREFE_OB): New.
(M_SCE_AB, M_SCE_OB): New.
(M_SBE_OB, M_SBE_AB): New.
(M_SHE_OB, M_SHE_AB): New.
(M_SWE_OB, M_SWE_AB): New.
(M_SWLE_AB, M_SWLE_OB): New.
(M_SWRE_AB, M_SWRE_OB): New.
(MICROMIPSOP_SH_EVAOFFSET): Define.
(MICROMIPSOP_MASK_EVAOFFSET): Define.
opcodes/
* micromips-opc.c (EVA): Define.
(TLBINV): Define.
(micromips_opcodes): Add EVA opcodes.
* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
(print_insn_args): Handle EVA offsets.
(print_insn_micromips): Likewise.
* mips-opc.c (EVA): Define.
(TLBINV): Define.
(mips_builtin_opcodes): Add EVA opcodes.
2013-06-18 06:59:10 +08:00
|
|
|
|
2013-06-17 Catherine Moore <clm@codesourcery.com>
|
|
|
|
|
|
Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
Chao-Ying Fu <fu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_set_options): Add ase_eva.
|
|
|
|
|
|
(mips_set_options mips_opts): Add ase_eva.
|
|
|
|
|
|
(file_ase_eva): Declare.
|
|
|
|
|
|
(ISA_SUPPORTS_EVA_ASE): Define.
|
|
|
|
|
|
(IS_SEXT_9BIT_NUM): Define.
|
|
|
|
|
|
(MIPS_CPU_ASE_EVA): Define.
|
|
|
|
|
|
(is_opcode_valid): Add support for ase_eva.
|
|
|
|
|
|
(macro_build): Likewise.
|
|
|
|
|
|
(macro): Likewise.
|
|
|
|
|
|
(validate_mips_insn): Likewise.
|
|
|
|
|
|
(validate_micromips_insn): Likewise.
|
|
|
|
|
|
(mips_ip): Likewise.
|
|
|
|
|
|
(options): Add OPTION_EVA and OPTION_NO_EVA.
|
|
|
|
|
|
(md_longopts): Add -meva and -mno-eva.
|
|
|
|
|
|
(md_parse_option): Process new options.
|
|
|
|
|
|
(mips_after_parse_args): Check for valid EVA combinations.
|
|
|
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|
(s_mipsset): Likewise.
|
|
|
|
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|
|
2013-06-14 21:30:28 +08:00
|
|
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|
2013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
|
|
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|
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|
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|
|
* dwarf2dbg.h (dwarf2_move_insn): Declare.
|
|
|
|
|
|
* dwarf2dbg.c (line_subseg): Add pmove_tail.
|
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|
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|
(get_line_subseg): Add create_p argument. Initialize pmove_tail.
|
|
|
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|
|
(dwarf2_gen_line_info_1): Update call accordingly.
|
|
|
|
|
|
(dwarf2_move_insn): New function.
|
|
|
|
|
|
* config/tc-mips.c (append_insn): Use dwarf2_move_insn.
|
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|
2013-06-14 21:24:41 +08:00
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2013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
|
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|
Revert:
|
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|
2011-09-05 Richard Sandiford <rdsandiford@googlemail.com>
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PR gas/13024
|
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* dwarf2dbg.c (pending_lines, pending_lines_tail): New variables.
|
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|
(dwarf2_gen_line_info_1): Delete.
|
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|
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|
(dwarf2_push_line, dwarf2_flush_pending_lines): New functions.
|
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(dwarf2_gen_line_info, dwarf2_emit_label): Use them.
|
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|
(dwarf2_consume_line_info): Call dwarf2_flush_pending_lines.
|
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(dwarf2_directive_loc): Push previous .locs instead of generating
|
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|
them immediately.
|
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2013-06-14 04:58:44 +08:00
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2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
|
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|
|
* config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips.
|
|
|
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|
|
(ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips.
|
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|
2013-06-13 16:53:35 +08:00
|
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|
2013-06-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
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|
|
PR gas/15602
|
|
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|
|
* config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define.
|
|
|
|
|
|
* config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New
|
|
|
|
|
|
function. Generates an error if the adjusted offset is out of a
|
|
|
|
|
|
16-bit range.
|
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|
|
2013-06-13 07:11:57 +08:00
|
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|
2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
|
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|
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|
|
* config/tc-nios2.c (md_apply_fix): Mask constant
|
|
|
|
|
|
BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
|
|
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|
|
2013-06-11 02:15:48 +08:00
|
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|
2013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (append_insn): Don't do branch relaxation for
|
|
|
|
|
|
MIPS-3D instructions either.
|
|
|
|
|
|
(md_convert_frag): Update the COPx branch mask accordingly.
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
|
|
|
|
|
|
option.
|
|
|
|
|
|
* doc/as.texinfo (Overview): Add --relax-branch and
|
|
|
|
|
|
--no-relax-branch.
|
|
|
|
|
|
* doc/c-mips.texi (MIPS Opts): Document --relax-branch and
|
|
|
|
|
|
--no-relax-branch.
|
|
|
|
|
|
|
2013-06-10 09:04:42 +08:00
|
|
|
|
2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
|
|
|
|
|
|
|
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|
|
|
|
* config/tc-nios2.c (nios2_parse_args): Allow trap argument to
|
|
|
|
|
|
omitted.
|
|
|
|
|
|
|
gas/
2013-06-08 Catherine Moore <clm@codesourcery.com>
* config/tc-mips.c (is_opcode_valid): Build ASE mask.
(is_opcode_valid_16): Pass ase value to opcode_is_member.
(append_insn): Change INSN_xxxx to ASE_xxxx.
include/
2013-06-08 Catherine Moore <clm@codesourcery.com>
* opcode/mips.h (mips_opcode): Add ase field.
(INSN_ASE_MASK): Delete.
(INSN_DSP): Rename to ASE_DSP. Provide new value.
(INSN_DSPR2): Rename to ASE_DSPR2. Provide new value.
(INSN_MCU): Rename to ASE_MCU. Provide new value.
(INSN_MDMX): Rename to ASE_MDMX. Provide new value.
(INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value.
(INSN_MT): Rename to ASE_MT. Provide new value.
(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value.
(INSN_VIRT): Rename to ASE_VIRT. Provide new value.
(INSN_VIRT64): Rename to ASE_VIRT64. Provide new value.
(opcode_is_member): Add ase argument. Check ase.
opcodes/
2013-06-08 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (D32, D33, MC): Update definitions.
(micromips_opcodes): Initialize ase field.
* mips-dis.c (mips_arch_choice): Add ase field.
(mips_arch_choices): Initialize ase field.
(set_default_mips_dis_options): Declare and setup mips_ase.
* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
MT32, MC): Update definitions.
(mips_builtin_opcodes): Initialize ase field.
2013-06-08 18:22:55 +08:00
|
|
|
|
2013-06-08 Catherine Moore <clm@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (is_opcode_valid): Build ASE mask.
|
|
|
|
|
|
(is_opcode_valid_16): Pass ase value to opcode_is_member.
|
|
|
|
|
|
(append_insn): Change INSN_xxxx to ASE_xxxx.
|
|
|
|
|
|
|
2013-06-01 15:14:44 +08:00
|
|
|
|
2013-06-01 George Thomas <george.thomas@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-avr.c: Change ISA for devices with USB support to
|
|
|
|
|
|
AVR_ISA_XMEGAU
|
|
|
|
|
|
|
2013-06-01 01:27:28 +08:00
|
|
|
|
2013-05-31 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (md_begin): Don't align text/data/bss sections
|
|
|
|
|
|
for ELF.
|
|
|
|
|
|
|
2013-06-01 01:04:53 +08:00
|
|
|
|
2013-05-31 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
gas/
|
|
|
|
|
|
* config/tc-mips.c (s_ehword): New.
|
|
|
|
|
|
|
2013-05-31 04:27:21 +08:00
|
|
|
|
2013-05-30 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH.
|
|
|
|
|
|
|
2013-05-30 00:22:14 +08:00
|
|
|
|
2013-05-29 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* write.c (resolve_reloc_expr_symbols): On REL targets don't
|
|
|
|
|
|
convert relocs who have no relocatable field either. Rephrase
|
|
|
|
|
|
the conditional so that the PC-relative check is only applied
|
|
|
|
|
|
for REL targets.
|
|
|
|
|
|
|
2013-05-29 06:19:34 +08:00
|
|
|
|
2013-05-28 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (macro) <ld>: Don't use $zero for address
|
|
|
|
|
|
calculation.
|
|
|
|
|
|
|
2013-05-29 00:39:51 +08:00
|
|
|
|
2013-05-28 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (reloc_table): Update to use
|
2013-06-25 05:05:30 +08:00
|
|
|
|
BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
|
2013-05-29 00:39:51 +08:00
|
|
|
|
BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE.
|
|
|
|
|
|
(md_apply_fix): Likewise.
|
|
|
|
|
|
(aarch64_force_relocation): Likewise.
|
|
|
|
|
|
|
2013-05-28 22:58:52 +08:00
|
|
|
|
2013-05-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (it_fsm_post_encode): Improve
|
|
|
|
|
|
warning messages about deprecated IT block formats.
|
|
|
|
|
|
|
2013-05-28 17:43:42 +08:00
|
|
|
|
2013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (md_apply_fix): Move value range checking
|
|
|
|
|
|
inside fx_done condition.
|
|
|
|
|
|
|
2013-05-23 02:08:26 +08:00
|
|
|
|
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.
|
|
|
|
|
|
|
opcodes/
* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
XLS_MASK, PPCVSX2): New defines.
(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
<lxvx, stxvx>: New extended mnemonics.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
and clean up warning when using PRINT_OPCODE_TABLE.
gas/testsuite/
* gas/ppc/altivec2.d <bcdadd., bcdadd., vaddcuq, vaddecuq, vaddeuqm,
vaddudm, vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh,
vclzw, vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud.,
veqv, vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw,
vmuleuw, vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast,
vorc, vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd,
vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm,
vsubudm, vsubuqm, vupkhsw, vupklsw>: Add new tests.
* gas/ppc/altivec2.s: Likewise.
* gas/ppc/power8.d <bcdadd., bcdsub., bctar, bctarl, clrbhrb, fmrgew,
fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe, mfvsrd, mfvsrwz,
msgclrp, msgsndp, mtsle, mtvsrd, mtvsrwa, mtvsrwz, pbt., rfebb,
stqcx., stxsiwx, stxsspx, vaddcuq, vaddecuq, vaddeuqm, vaddudm,
vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh, vclzw,
vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv,
vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgow, vmulesw, vmuleuw,
vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc,
vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd,
vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm,
vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp, xscvdpspn, xscvspdpn,
xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp, xsmaddmsp, xsmsubasp,
xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp,
xsresp, xsrsp, xsrsqrtesp, xssqrtsp, xssubsp, xxleqv, xxlnand,
xxlorc>: Add new tests.
* gas/ppc/power8.s Likewise.
* gas/ppc/vsx.d <lxvd2x, stxvd2x>: Add new tests.
* gas/ppc/vsx.s Likewise.
* gas/ppc/vsx2.d: New test file.
* gas/ppc/vsx2.s: Likewise.
* gas/ppc/ppc.exp: Run it.
2013-05-21 09:36:46 +08:00
|
|
|
|
2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
|
|
|
|
|
|
and clean up warning when using PRINT_OPCODE_TABLE.
|
|
|
|
|
|
|
2013-05-20 18:16:31 +08:00
|
|
|
|
2013-05-20 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (md_apply_fix): Hoist code common to insn
|
|
|
|
|
|
and data fixups performing shift/high adjust/sign extension on
|
|
|
|
|
|
fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size
|
|
|
|
|
|
when writing data fixups rather than recalculating size.
|
|
|
|
|
|
|
2013-05-17 00:47:14 +08:00
|
|
|
|
2013-05-16 Jan-Benedict Glaw <jbglaw@lug-owl.de>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-msp430.texi: Fix typo.
|
|
|
|
|
|
|
2013-05-16 23:41:40 +08:00
|
|
|
|
2013-05-16 Tristan Gingold <gingold@adacore.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (ppc_is_toc_sym): Symbols of class XMC_TC
|
|
|
|
|
|
are also TOC symbols.
|
|
|
|
|
|
|
2013-05-16 21:19:40 +08:00
|
|
|
|
2013-05-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-msp430.c: Make -mmcu recognise more part numbers.
|
|
|
|
|
|
Add -mcpu command to specify core type.
|
2013-05-17 00:47:14 +08:00
|
|
|
|
* doc/c-msp430.texi: Update documentation.
|
2013-05-16 21:19:40 +08:00
|
|
|
|
|
binutils/ChangeLog:
* doc/binutils.texi: Document -Mvirt disassembler option.
gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".
gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.
include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
2013-05-10 09:08:48 +08:00
|
|
|
|
2013-05-09 Andrew Pinski <apinski@cavium.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
|
|
|
|
|
|
(mips_opts): Update for the new field.
|
|
|
|
|
|
(file_ase_virt): New variable.
|
|
|
|
|
|
(ISA_SUPPORTS_VIRT_ASE): New macro.
|
|
|
|
|
|
(ISA_SUPPORTS_VIRT64_ASE): New macro.
|
|
|
|
|
|
(MIPS_CPU_ASE_VIRT): New define.
|
|
|
|
|
|
(is_opcode_valid): Handle ase_virt.
|
|
|
|
|
|
(macro_build): Handle "+J".
|
|
|
|
|
|
(validate_mips_insn): Likewise.
|
|
|
|
|
|
(mips_ip): Likewise.
|
|
|
|
|
|
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
|
|
|
|
|
|
(md_longopts): Add mvirt and mnovirt
|
|
|
|
|
|
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
|
|
|
|
|
|
(mips_after_parse_args): Handle ase_virt field.
|
|
|
|
|
|
(s_mipsset): Handle "virt" and "novirt".
|
|
|
|
|
|
(mips_elf_final_processing): Add a comment about virt ASE might need
|
|
|
|
|
|
a new flag.
|
|
|
|
|
|
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
|
|
|
|
|
|
* doc/c-mips.texi: Document -mvirt and -mno-virt.
|
|
|
|
|
|
Document ".set virt" and ".set novirt".
|
|
|
|
|
|
|
2013-05-09 12:01:53 +08:00
|
|
|
|
2013-05-09 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (md_apply_fix): Sign extend fieldval under
|
|
|
|
|
|
control of operand flag bits.
|
|
|
|
|
|
|
2013-05-07 07:36:48 +08:00
|
|
|
|
2013-05-07 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (PPC_VLE_SPLIT16A): Delete unused macro.
|
|
|
|
|
|
(PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise.
|
|
|
|
|
|
(PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise.
|
|
|
|
|
|
(PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise.
|
|
|
|
|
|
(md_apply_fix): Set fx_no_overflow for assorted relocations.
|
|
|
|
|
|
Shift and sign-extend fieldval for use by some VLE reloc
|
|
|
|
|
|
operand->insert functions.
|
|
|
|
|
|
|
2013-05-06 23:25:45 +08:00
|
|
|
|
2013-05-06 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
Catherine Moore <clm@codesourcery.com>
|
|
|
|
|
|
|
2013-05-07 07:36:48 +08:00
|
|
|
|
* config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL.
|
|
|
|
|
|
(limited_pcrel_reloc_p): Likewise.
|
2013-05-06 23:25:45 +08:00
|
|
|
|
(md_apply_fix): Likewise.
|
|
|
|
|
|
(tc_gen_reloc): Likewise.
|
|
|
|
|
|
|
2013-05-06 23:00:01 +08:00
|
|
|
|
2013-05-06 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (limited_pcrel_reloc_p): New function.
|
|
|
|
|
|
(mips_fix_adjustable): Adjust pc-relative check to use
|
|
|
|
|
|
limited_pc_reloc_p.
|
|
|
|
|
|
|
2013-05-03 06:30:11 +08:00
|
|
|
|
2013-05-02 Richard Sandiford <rdsandiford@googlemail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries.
|
|
|
|
|
|
(s_mips_stab): Do not restrict to stabn only.
|
|
|
|
|
|
|
2013-05-03 05:06:15 +08:00
|
|
|
|
2013-05-02 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-msp430.c: Add support for the MSP430X architecture.
|
|
|
|
|
|
Add code to insert a NOP instruction after any instruction that
|
|
|
|
|
|
might change the interrupt state.
|
|
|
|
|
|
Add support for the LARGE memory model.
|
|
|
|
|
|
Add code to initialise the .MSP430.attributes section.
|
|
|
|
|
|
* config/tc-msp430.h: Add support for the MSP430X architecture.
|
|
|
|
|
|
* doc/c-msp430.texi: Document the new -mL and -mN command line
|
|
|
|
|
|
options.
|
|
|
|
|
|
* NEWS: Mention support for the MSP430X architecture.
|
|
|
|
|
|
|
2013-05-02 01:27:46 +08:00
|
|
|
|
2013-05-01 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt: Replace alpha*-*-linuxecoff* pattern with
|
|
|
|
|
|
alpha*-*-linux*ecoff*.
|
|
|
|
|
|
|
2013-05-01 09:02:01 +08:00
|
|
|
|
2013-04-30 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (mips_ip): Add sizelo.
|
|
|
|
|
|
For "+C", "+G", and "+H", set sizelo and compare against it.
|
|
|
|
|
|
|
2013-04-29 21:38:59 +08:00
|
|
|
|
2013-04-29 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* as.c (Options): Add -gdwarf-sections.
|
|
|
|
|
|
(parse_args): Likewise.
|
|
|
|
|
|
* as.h (flag_dwarf_sections): Declare.
|
|
|
|
|
|
* dwarf2dbg.c (emit_fixed_inc_line_addr): Skip section changes.
|
|
|
|
|
|
(process_entries): When -gdwarf-sections is enabled generate
|
|
|
|
|
|
fragmentary .debug_line sections.
|
|
|
|
|
|
(out_debug_line): Set the section for the .debug_line section end
|
|
|
|
|
|
symbol.
|
|
|
|
|
|
* doc/as.texinfo: Document -gdwarf-sections.
|
|
|
|
|
|
* NEWS: Mention -gdwarf-sections.
|
|
|
|
|
|
|
2013-04-27 03:31:15 +08:00
|
|
|
|
2013-04-26 Christian Groessler <chris@groessler.org>
|
2013-04-27 03:21:25 +08:00
|
|
|
|
|
|
|
|
|
|
* config/tc-z8k.c (md_parse_option): Set z8k_target_from_cmdline
|
|
|
|
|
|
according to the target parameter. Don't call s_segm since s_segm
|
|
|
|
|
|
calls bfd_set_arch_mach using stdoutput, but stdoutput isn't
|
|
|
|
|
|
initialized yet.
|
|
|
|
|
|
(md_begin): Call s_segm according to target parameter from command
|
|
|
|
|
|
line.
|
|
|
|
|
|
|
2013-04-25 21:22:52 +08:00
|
|
|
|
2013-04-25 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.in: Allow little-endian linux.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
|
2013-04-25 04:51:58 +08:00
|
|
|
|
2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nios2.c (nios2_control_register_arg_p): Rename
|
|
|
|
|
|
"fstatus" control register to "eccinj".
|
|
|
|
|
|
|
2013-04-19 17:10:28 +08:00
|
|
|
|
2013-04-19 Kai Tietz <ktietz@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt (i386-*-cygwin): Handle x86_64 cygwin.
|
|
|
|
|
|
|
2013-04-15 18:30:23 +08:00
|
|
|
|
2013-04-15 Julian Brown <julian@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* expr.c (add_to_result, subtract_from_result): Make global.
|
|
|
|
|
|
* expr.h (add_to_result, subtract_from_result): Add prototypes.
|
|
|
|
|
|
* config/tc-sh.c (sh_optimize_expr): Use add_to_result,
|
|
|
|
|
|
subtract_from_result to handle extra bit of precision for .sleb128
|
|
|
|
|
|
directive operands.
|
|
|
|
|
|
|
2013-04-11 18:54:13 +08:00
|
|
|
|
2013-04-10 Julian Brown <julian@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* read.c (convert_to_bignum): Add sign parameter. Use it
|
|
|
|
|
|
instead of X_unsigned to determine sign of resulting bignum.
|
|
|
|
|
|
(emit_expr): Pass extra argument to convert_to_bignum.
|
|
|
|
|
|
(emit_leb128_expr): Use X_extrabit instead of X_unsigned. Pass
|
|
|
|
|
|
X_extrabit to convert_to_bignum.
|
|
|
|
|
|
(parse_bitfield_cons): Set X_extrabit.
|
|
|
|
|
|
* expr.c (make_expr_symbol, expr_build_uconstant, operand):
|
|
|
|
|
|
Initialise X_extrabit field as appropriate.
|
|
|
|
|
|
(add_to_result): New.
|
|
|
|
|
|
(subtract_from_result): New.
|
|
|
|
|
|
(expr): Use above.
|
|
|
|
|
|
* expr.h (expressionS): Add X_extrabit field.
|
|
|
|
|
|
|
2013-04-10 21:20:05 +08:00
|
|
|
|
2013-04-10 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base
|
|
|
|
|
|
register being PC when is_t or writeback, and use distinct
|
|
|
|
|
|
diagnostic for the latter case.
|
|
|
|
|
|
|
2013-04-10 21:18:33 +08:00
|
|
|
|
2013-04-10 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-arm.c (parse_operands): Re-write
|
|
|
|
|
|
po_barrier_or_imm().
|
|
|
|
|
|
(do_barrier): Remove bogus constraint().
|
|
|
|
|
|
(do_t_barrier): Remove.
|
|
|
|
|
|
|
2013-04-09 23:39:37 +08:00
|
|
|
|
2013-04-09 Joerg Wunsch <joerg.wunsch@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-avr.c (mcu_types): Add ATmega64RFR2,
|
|
|
|
|
|
ATmega644RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega256RFR2,
|
|
|
|
|
|
ATmega2564RFR2
|
|
|
|
|
|
* gas/doc/c-avr.texi (-mmcu documentation): Likewise.
|
|
|
|
|
|
|
2013-04-09 19:07:06 +08:00
|
|
|
|
2013-04-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-arm.c (do_vmrs): Accept all control registers.
|
|
|
|
|
|
Use local variable Rt in more places.
|
|
|
|
|
|
(do_vmsr): Accept all control registers.
|
|
|
|
|
|
|
2013-04-09 19:05:45 +08:00
|
|
|
|
2013-04-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
|
|
|
|
|
|
if there was none specified for moves between scalar and core
|
|
|
|
|
|
register.
|
|
|
|
|
|
|
2013-04-09 19:04:24 +08:00
|
|
|
|
2013-04-09 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the
|
|
|
|
|
|
NEON_ALL_LANES case.
|
|
|
|
|
|
|
2013-04-08 19:07:38 +08:00
|
|
|
|
2013-04-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-arm.c (do_neon_ldr_str): Correct disgnostics for
|
|
|
|
|
|
PC-relative VSTR.
|
|
|
|
|
|
|
2013-04-08 19:06:30 +08:00
|
|
|
|
2013-04-08 Jan Beulich <jbeulich@suse.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-arm.c (reg_names): Convert duplicate SP_fiq
|
|
|
|
|
|
entry to sp_fiq.
|
|
|
|
|
|
|
2013-04-03 10:48:37 +08:00
|
|
|
|
2013-04-03 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/as.texinfo: Add support to generate man options for h8300.
|
|
|
|
|
|
* doc/c-h8300.texi: Likewise.
|
|
|
|
|
|
|
2013-03-28 19:00:15 +08:00
|
|
|
|
2013-03-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_cpus): Add support for Cortex-A53 and
|
|
|
|
|
|
Cortex-A57.
|
|
|
|
|
|
|
2013-03-27 19:43:37 +08:00
|
|
|
|
2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/15068
|
|
|
|
|
|
* config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array.
|
|
|
|
|
|
|
2013-03-26 21:49:12 +08:00
|
|
|
|
2013-03-26 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
2013-03-26 22:16:59 +08:00
|
|
|
|
PR gas/15295
|
|
|
|
|
|
* listing.c (rebuffer_line): Rewrite to avoid seeking back to the
|
|
|
|
|
|
start of the file each time.
|
|
|
|
|
|
|
2013-03-26 21:49:12 +08:00
|
|
|
|
PR gas/15178
|
|
|
|
|
|
* config/tc-sparc.h (ELF_TARGET_FORMAT): Set to elf32-sparc for
|
|
|
|
|
|
FreeBSD targets.
|
|
|
|
|
|
|
2013-03-26 17:13:17 +08:00
|
|
|
|
2013-03-26 Douglas B Rupp <rupp@gnat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment
|
|
|
|
|
|
after fixup.
|
|
|
|
|
|
|
2013-03-22 02:39:35 +08:00
|
|
|
|
2013-03-21 Will Newton <will.newton@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all
|
|
|
|
|
|
pc-relative str instructions in Thumb mode.
|
|
|
|
|
|
|
2013-03-22 00:08:07 +08:00
|
|
|
|
2013-03-21 Michael Schewe <michael.schewe@gmx.net>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov
|
|
|
|
|
|
@(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc
|
|
|
|
|
|
R_H8_DISP32A16.
|
|
|
|
|
|
* config/tc-h8300.h: Remove duplicated defines.
|
|
|
|
|
|
|
2013-03-21 22:47:34 +08:00
|
|
|
|
2013-03-21 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15282
|
|
|
|
|
|
* tc-avr.c (mcu_has_3_byte_pc): New function.
|
|
|
|
|
|
(tc_cfi_frame_initial_instructions): Call it to find return
|
|
|
|
|
|
address size.
|
|
|
|
|
|
|
2013-03-21 00:36:34 +08:00
|
|
|
|
2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15095
|
|
|
|
|
|
* config/tc-tic6x.c (tic6x_try_encode): Handle
|
|
|
|
|
|
tic6x_coding_dreg_(msb|lsb) field coding types and use it to
|
|
|
|
|
|
encode register pair numbers when required.
|
|
|
|
|
|
|
2013-03-15 23:53:39 +08:00
|
|
|
|
2013-03-15 Will Newton <will.newton@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register
|
|
|
|
|
|
in vstr in Thumb mode for pre-ARMv7 cores.
|
|
|
|
|
|
|
2013-03-15 00:17:45 +08:00
|
|
|
|
2013-03-14 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-arc.texi (ARC Directives): Revert last change and use
|
|
|
|
|
|
@itemize instead of @table.
|
|
|
|
|
|
* doc/c-arm.texi (ARM-Instruction-Set): Likewise.
|
|
|
|
|
|
|
2013-03-14 18:23:13 +08:00
|
|
|
|
2013-03-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15273
|
|
|
|
|
|
* config/tc-arm.c (do_co_reg): Do not call check_obsolete with a
|
|
|
|
|
|
NULL message, instead just check ARM_CPU_IS_ANY directly.
|
|
|
|
|
|
|
2013-03-14 18:00:46 +08:00
|
|
|
|
2013-03-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15212
|
2013-03-15 00:17:45 +08:00
|
|
|
|
* doc/c-arc.texi (ARC Directives): Use @code instead of @bullet
|
2013-03-14 18:00:46 +08:00
|
|
|
|
for table format.
|
|
|
|
|
|
* doc/c-arm.texi (ARM-Instruction-Set): Likewise. Also add text
|
|
|
|
|
|
to the @item directives.
|
|
|
|
|
|
(ARM-Neon-Alignment): Move to correct place in the document.
|
|
|
|
|
|
* doc/c-cr16.texi (CR16 Operand Qualifiers): Fix up table
|
|
|
|
|
|
formatting.
|
|
|
|
|
|
* doc/c-tic54x.texi (TIC54X-Subsyms): Correct use of
|
|
|
|
|
|
@smallexample.
|
|
|
|
|
|
|
2013-03-13 03:18:57 +08:00
|
|
|
|
2013-03-12 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nios2.c (nios2_consume_arg): Delete 'k' case. Add 'o'
|
|
|
|
|
|
case. Add default BAD_CASE to switch.
|
|
|
|
|
|
|
2013-03-12 10:41:26 +08:00
|
|
|
|
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-nios2.c (nios2_assemble_args_ds): New function.
|
|
|
|
|
|
(nios2_arg_info_structs): Add "d,s" and "d,s,E" entries.
|
|
|
|
|
|
|
2013-03-11 19:09:33 +08:00
|
|
|
|
2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (crc_ext_armv8): New feature set.
|
|
|
|
|
|
(UNPRED_REG): New macro.
|
|
|
|
|
|
(do_crc32_1): New function.
|
|
|
|
|
|
(do_crc32b, do_crc32h, do_crc32w, do_crc32cb,
|
|
|
|
|
|
do_crc32ch, do_crc32cw): Likewise.
|
|
|
|
|
|
(TUEc): New macro.
|
|
|
|
|
|
(insns): Add entries for crc32 mnemonics.
|
|
|
|
|
|
(arm_extensions): Add entry for crc.
|
|
|
|
|
|
|
2013-03-08 18:17:00 +08:00
|
|
|
|
2013-03-08 Chung-Lin Tang <cltang@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* write.h (struct fix): Add fx_dot_frag field.
|
|
|
|
|
|
(dot_frag): Declare.
|
|
|
|
|
|
* write.c (dot_frag): New variable.
|
|
|
|
|
|
(fix_new_internal): Set fx_dot_frag field with dot_frag.
|
|
|
|
|
|
(fixup_segment): Base calculation of fx_offset with fx_dot_frag.
|
|
|
|
|
|
* expr.c (expr): Save value of frag_now in dot_frag when setting
|
|
|
|
|
|
dot_value.
|
|
|
|
|
|
* read.c (emit_expr): Likewise. Delete comments.
|
|
|
|
|
|
|
2013-03-08 05:40:06 +08:00
|
|
|
|
2013-03-07 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (flag_code_names): Removed.
|
|
|
|
|
|
(i386_index_check): Rewrote.
|
|
|
|
|
|
|
2013-03-06 00:31:44 +08:00
|
|
|
|
2013-03-05 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern';
|
|
|
|
|
|
add comment.
|
|
|
|
|
|
(aarch64_double_precision_fmovable): New function.
|
|
|
|
|
|
(parse_aarch64_imm_float): Add parameter 'dp_p'; call the new
|
|
|
|
|
|
function; handle hexadecimal representation of IEEE754 encoding.
|
|
|
|
|
|
(parse_operands): Update the call to parse_aarch64_imm_float.
|
|
|
|
|
|
|
2013-03-01 05:08:04 +08:00
|
|
|
|
2013-02-28 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (_i386_insn): Replace have_hle with hle_prefix.
|
|
|
|
|
|
(check_hle): Updated.
|
|
|
|
|
|
(md_assemble): Likewise.
|
|
|
|
|
|
(parse_insn): Likewise.
|
|
|
|
|
|
|
2013-03-01 04:50:19 +08:00
|
|
|
|
2013-02-28 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (_i386_insn): Add rep_prefix.
|
2013-03-15 00:17:45 +08:00
|
|
|
|
(md_assemble): Check if REP prefix is OK.
|
2013-03-01 04:50:19 +08:00
|
|
|
|
(parse_insn): Remove expecting_string_instruction. Set
|
|
|
|
|
|
i.rep_prefix.
|
|
|
|
|
|
|
2013-03-01 03:18:40 +08:00
|
|
|
|
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (aarch64_features): Add the 'crc' option.
|
|
|
|
|
|
|
2013-03-01 02:51:05 +08:00
|
|
|
|
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
|
|
|
|
|
|
for system registers.
|
|
|
|
|
|
|
2013-02-28 05:39:20 +08:00
|
|
|
|
2013-02-27 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-rl78.c (reloc_function): Add %code -> BFD_RELOC_RL78_CODE.
|
|
|
|
|
|
(rl78_op): Handle %code().
|
|
|
|
|
|
(rl78_cons_fix_new): Likewise, but ignore for 20-bit operands.
|
|
|
|
|
|
(tc_gen_reloc): Likwise; convert to a computed reloc.
|
|
|
|
|
|
(md_apply_fix): Likewise.
|
|
|
|
|
|
|
2013-02-26 02:41:06 +08:00
|
|
|
|
2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/rl78-parse.y: Fix encoding of DIVWU insn.
|
|
|
|
|
|
|
2013-02-25 10:53:41 +08:00
|
|
|
|
2013-02-25 Terry Guo <terry.guo@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (arm_cpus): Add cortex-r7 entry.
|
|
|
|
|
|
* doc/c-arm.texi: Add cortex-r7 and missing cortex-r5 to
|
|
|
|
|
|
list of accepted CPUs.
|
|
|
|
|
|
|
2013-02-20 03:10:31 +08:00
|
|
|
|
2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15159
|
|
|
|
|
|
* config/tc-i386.c (cpu_arch): Add ".smap".
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-i386.texi: Document smap.
|
|
|
|
|
|
|
2013-02-19 07:27:23 +08:00
|
|
|
|
2013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (s_cpload): Call mips_mark_labels and set
|
|
|
|
|
|
mips_assembling_insn appropriately.
|
|
|
|
|
|
(s_cpsetup, s_cprestore, s_cpreturn, s_cpadd): Likewise.
|
|
|
|
|
|
|
2013-02-18 22:02:02 +08:00
|
|
|
|
2013-02-18 Maciej W. Rozycki <macro@codesourcery.com>
|
|
|
|
|
|
|
2013-02-18 22:02:47 +08:00
|
|
|
|
* config/tc-mips.c (append_insn): Correct indentation, remove
|
2013-02-18 22:02:02 +08:00
|
|
|
|
extraneous braces.
|
|
|
|
|
|
|
2013-02-15 18:07:47 +08:00
|
|
|
|
2013-02-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
2013-02-20 03:10:31 +08:00
|
|
|
|
* config/tc-arm.c (do_neon_mov): Break on NS_NULL.
|
2013-02-15 18:07:47 +08:00
|
|
|
|
|
2013-02-15 17:36:32 +08:00
|
|
|
|
2013-02-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* configure.tgt: Add nios2-*-rtems*.
|
|
|
|
|
|
|
2013-02-15 02:12:51 +08:00
|
|
|
|
2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-aarch64.c (md_begin): Change to check if 'name' is
|
|
|
|
|
|
NULL.
|
|
|
|
|
|
|
gas/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
(macro): Use it. Assert that trunc.w.s is not used for r5900.
opcodes/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
single-float. Disable ll, lld, sc and scd for EE. Disable the
trunc.w.s macro for EE.
gas/testsuite/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/24k-triple-stores-2.d, gas/mips/24k-triple-stores-2.s,
gas/mips/micromips@24k-triple-stores-2.d: Move "sc" tests to...
* gas/mips/24k-triple-stores-2-llsc.d,
gas/mips/24k-triple-stores-2-llsc.s,
gas/mips/micromips@24k-triple-stores-2-llsc.d: ...these new tests.
* gas/mips/r5900-full.d, gas/mips/r5900-full.s: Verify that the
MIPS ISA level can be upgraded to support ll, sc, lld and scd.
* gas/mips/l_d-single.d, gas/mips/s_d-single.d,
gas/mips/r5900-nollsc.l, gas/mips/r5900-nollsc.s: New tests.
* gas/mips/mips.exp: Update accordingly. Add "nollsc" to r5900
properties.
2013-02-09 18:24:20 +08:00
|
|
|
|
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
|
|
|
|
|
|
(macro): Use it. Assert that trunc.w.s is not used for r5900.
|
|
|
|
|
|
|
2013-02-09 00:57:41 +08:00
|
|
|
|
2013-02-08 Yi-Hsiu, Hsu <ahsu@marvell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* gas/config/tc-arm.c (arm_cpus): Add support for mcpu=marvell-pj4
|
|
|
|
|
|
core.
|
|
|
|
|
|
|
2013-02-07 07:22:26 +08:00
|
|
|
|
2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
|
2013-02-20 03:10:31 +08:00
|
|
|
|
Andrew Jenner <andrew@codesourcery.com>
|
2013-02-07 07:22:26 +08:00
|
|
|
|
|
|
|
|
|
|
Based on patches from Altera Corporation.
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-nios2.c.
|
|
|
|
|
|
(TARGET_CPU_HFILES): Add config/tc-nios2.h.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* configure.tgt: Add case for nios2*-linux*.
|
|
|
|
|
|
* config/obj-elf.c: Conditionally include elf/nios2.h.
|
|
|
|
|
|
* config/tc-nios2.c: New file.
|
|
|
|
|
|
* config/tc-nios2.h: New file.
|
|
|
|
|
|
* doc/Makefile.am (CPU_DOCS): Add c-nios2.texi.
|
|
|
|
|
|
* doc/Makefile.in: Regenerated.
|
|
|
|
|
|
* doc/all.texi: Set NIOSII.
|
|
|
|
|
|
* doc/as.texinfo (Overview): Add Nios II options.
|
|
|
|
|
|
(Machine Dependencies): Include c-nios2.texi.
|
|
|
|
|
|
* doc/c-nios2.texi: New file.
|
|
|
|
|
|
* NEWS: Note Altera Nios II support.
|
|
|
|
|
|
|
2013-02-06 07:02:54 +08:00
|
|
|
|
2013-02-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/14255
|
|
|
|
|
|
* config/tc-avr.h (TC_VALIDATE_FIX): Mark symbol used by reloc.
|
|
|
|
|
|
Don't skip fixups with fx_subsy non-NULL.
|
|
|
|
|
|
* config/tc-avr.c (tc_gen_reloc): Don't specially handle fixups
|
|
|
|
|
|
with fx_subsy non-NULL.
|
|
|
|
|
|
|
2013-02-05 04:29:21 +08:00
|
|
|
|
2013-02-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* doc/c-metag.texi: Add "@c man" markers.
|
|
|
|
|
|
|
2013-02-04 20:34:17 +08:00
|
|
|
|
2013-02-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* write.c (fixup_segment): Return void. Delete seg_reloc_count
|
|
|
|
|
|
related code.
|
|
|
|
|
|
(TC_ADJUST_RELOC_COUNT): Delete.
|
|
|
|
|
|
* config/tc-i960.h (TC_ADJUST_RELOC_COUNT): Delete.
|
|
|
|
|
|
|
2013-02-04 14:03:10 +08:00
|
|
|
|
2013-02-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2013-01-30 21:21:01 +08:00
|
|
|
|
2013-01-30 Markos Chandras <markos.chandras@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-metag.c: Make SWAP instruction less permissive with
|
|
|
|
|
|
its operands.
|
|
|
|
|
|
|
2013-01-30 06:17:53 +08:00
|
|
|
|
2013-01-29 DJ Delorie <dj@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-rl78.c (rl78_cons_fix_new): Handle user-specified
|
|
|
|
|
|
relocs in .word/.etc statements.
|
|
|
|
|
|
|
2013-01-30 01:33:22 +08:00
|
|
|
|
2013-01-29 Roland McGrath <mcgrathr@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-arm.c (md_apply_fix): Use as_bad_where for "bad
|
|
|
|
|
|
immediate value for 8-bit offset" error so it shows line info.
|
|
|
|
|
|
|
2013-01-25 10:02:21 +08:00
|
|
|
|
2013-01-24 Joseph Myers <joseph@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-ppc.c (md_assemble): Do not generate APUinfo sections
|
|
|
|
|
|
for 64-bit output.
|
|
|
|
|
|
|
2013-01-24 19:14:05 +08:00
|
|
|
|
2013-01-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-v850.c: Add support for e3v5 architecture.
|
|
|
|
|
|
* doc/c-v850.texi: Mention new support.
|
|
|
|
|
|
|
2013-01-23 20:01:12 +08:00
|
|
|
|
2013-01-23 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15039
|
|
|
|
|
|
* config/tc-avr.c: Include dwarf2dbg.h.
|
|
|
|
|
|
|
2013-01-19 00:37:08 +08:00
|
|
|
|
2013-01-18 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* config/tc-i386.c (reloc): Support size relocation only for ELF.
|
|
|
|
|
|
(tc_i386_fix_adjustable): Likewise.
|
|
|
|
|
|
(lex_got): Likewise.
|
|
|
|
|
|
(tc_gen_reloc): Likewise.
|
|
|
|
|
|
|
2013-01-18 00:09:44 +08:00
|
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2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
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* config/tc-aarch64.c (output_operand_error_record): Change to output
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the out-of-range error message as value-expected message if there is
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only one single value in the expected range.
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(programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
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LSL #0 as a programmer-friendly feature.
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2013-01-17 12:28:48 +08:00
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2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (reloc): Support BFD_RELOC_SIZE32.
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(tc_i386_fix_adjustable): Keep symbol for BFD_RELOC_32_SIZE and
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BFD_RELOC_64_SIZE relocations.
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(lex_got): Support "symbol@SIZE" and don't create GOT symbol
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for it.
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(tc_gen_reloc): Resolve BFD_RELOC_SIZE32 and BFD_RELOC_SIZE64
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relocations against local symbols.
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2013-01-16 14:12:46 +08:00
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2013-01-16 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (md_assemble <TE_PE>): Ignore line after
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finding some sort of toc syntax error, and break to avoid
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compiler uninit warning.
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2013-01-16 04:34:11 +08:00
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2013-01-15 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/15019
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* config/tc-i386.c (lex_got): Increment length by 1 if the
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relocation token is removed.
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2013-01-15 16:45:45 +08:00
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2013-01-15 Nick Clifton <nickc@redhat.com>
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* config/tc-v850.c (md_assemble): Allow signed values for
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V850E_IMMEDIATE.
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2013-01-12 05:12:34 +08:00
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2013-01-11 Sean Keys <skeys@ipdatasys.com>
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* config/tc-xgate.c (md_begin): Fix mistake made when going from
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2013-01-16 04:34:11 +08:00
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git to cvs.
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2013-01-12 05:12:34 +08:00
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include/opcode/
* ppc.h (PPC_OPCODE_POWER8): New define.
(PPC_OPCODE_HTM): Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
(SH6): Update.
<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
gas/
* doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* config/tc-ppc.c (md_show_usage): Likewise.
(ppc_handle_align): Handle power8's group ending nop.
gas/testsuite/
* gas/ppc/htm.d: New test.
* gas/ppc/htm.s: Likewise.
* gas/ppc/power8.d: Likewise.
* gas/ppc/power8.s: Likewise.
* gas/ppc/ppc.exp: Run them.
2013-01-11 10:25:36 +08:00
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2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
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* doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
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* doc/c-ppc.texi (PowerPC-Opts): Likewise.
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* config/tc-ppc.c (md_show_usage): Likewise.
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(ppc_handle_align): Handle power8's group ending nop.
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2013-01-11 06:15:05 +08:00
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2013-01-10 Sean Keys <skeys@ipdatasys.com>
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* config/tc-xgate.c (md_begin): Fix the printing of opcodes so
|
2013-01-16 04:34:11 +08:00
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that the assember exits after the opcodes have been printed.
|
2013-01-11 06:15:05 +08:00
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2013-01-11 03:51:55 +08:00
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2013-01-10 H.J. Lu <hongjiu.lu@intel.com>
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* app.c: Remove trailing white spaces.
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* as.c: Likewise.
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* as.h: Likewise.
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* cond.c: Likewise.
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* dw2gencfi.c: Likewise.
|
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* dwarf2dbg.h: Likewise.
|
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* ecoff.c: Likewise.
|
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* input-file.c: Likewise.
|
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* itbl-lex.h: Likewise.
|
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* output-file.c: Likewise.
|
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* read.c: Likewise.
|
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* sb.c: Likewise.
|
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* subsegs.c: Likewise.
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* symbols.c: Likewise.
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* write.c: Likewise.
|
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* config/tc-i386.c: Likewise.
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* doc/Makefile.am: Likewise.
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* doc/Makefile.in: Likewise.
|
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* doc/c-aarch64.texi: Likewise.
|
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* doc/c-alpha.texi: Likewise.
|
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* doc/c-arc.texi: Likewise.
|
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* doc/c-arm.texi: Likewise.
|
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* doc/c-avr.texi: Likewise.
|
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* doc/c-bfin.texi: Likewise.
|
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* doc/c-cr16.texi: Likewise.
|
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* doc/c-d10v.texi: Likewise.
|
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* doc/c-d30v.texi: Likewise.
|
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* doc/c-h8300.texi: Likewise.
|
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* doc/c-hppa.texi: Likewise.
|
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* doc/c-i370.texi: Likewise.
|
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|
* doc/c-i386.texi: Likewise.
|
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* doc/c-i860.texi: Likewise.
|
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* doc/c-m32c.texi: Likewise.
|
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|
* doc/c-m32r.texi: Likewise.
|
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|
* doc/c-m68hc11.texi: Likewise.
|
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|
* doc/c-m68k.texi: Likewise.
|
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|
* doc/c-microblaze.texi: Likewise.
|
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|
* doc/c-mips.texi: Likewise.
|
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|
* doc/c-msp430.texi: Likewise.
|
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|
* doc/c-mt.texi: Likewise.
|
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|
* doc/c-s390.texi: Likewise.
|
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|
* doc/c-score.texi: Likewise.
|
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|
* doc/c-sh.texi: Likewise.
|
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|
* doc/c-sh64.texi: Likewise.
|
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|
* doc/c-tic54x.texi: Likewise.
|
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|
* doc/c-tic6x.texi: Likewise.
|
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|
|
* doc/c-v850.texi: Likewise.
|
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|
|
* doc/c-xc16x.texi: Likewise.
|
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|
* doc/c-xgate.texi: Likewise.
|
|
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|
* doc/c-xtensa.texi: Likewise.
|
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|
* doc/c-z80.texi: Likewise.
|
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|
|
* doc/internals.texi: Likewise.
|
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|
|
|
2013-01-11 01:11:17 +08:00
|
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|
|
2013-01-10 Roland McGrath <mcgrathr@google.com>
|
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|
* hash.c (hash_new_sized): Make it global.
|
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|
* hash.h: Declare it.
|
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|
* macro.c (define_macro): Use hash_new_sized instead of hash_new,
|
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|
|
pass a small size.
|
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|
2013-01-10 17:49:22 +08:00
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|
2013-01-10 Will Newton <will.newton@imgtec.com>
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|
|
* Makefile.am: Add Meta.
|
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|
|
* Makefile.in: Regenerate.
|
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|
* config/tc-metag.c: New file.
|
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|
* config/tc-metag.h: New file.
|
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* configure.tgt: Add Meta.
|
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|
* doc/Makefile.am: Add Meta.
|
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|
* doc/Makefile.in: Regenerate.
|
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|
* doc/all.texi: Add Meta.
|
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|
* doc/as.texiinfo: Document Meta options.
|
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|
* doc/c-metag.texi: New file.
|
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|
2013-01-10 02:31:21 +08:00
|
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|
|
2013-01-09 Steve Ellcey <sellcey@mips.com>
|
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|
|
* config/tc-i386.c (md_begin): Remove 'internal Error' from as_fatal
|
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|
|
|
calls.
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|
|
* config/tc-mips.c (internalError): Remove, replace with abort.
|
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|
2013-01-09 02:17:10 +08:00
|
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|
2013-01-08 Yufeng Zhang <yufeng.zhang@arm.com>
|
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|
|
* config/tc-aarch64.c (parse_operands): Change to compare the result
|
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|
|
of function call 'parse_sys_reg' with 'PARSE_FAIL' instead of 'FALSE'.
|
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|
|
2013-01-07 20:49:12 +08:00
|
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|
|
2013-01-07 Nick Clifton <nickc@redhat.com>
|
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|
|
PR gas/14887
|
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|
|
* config/tc-arm.c (skip_past_char): Skip whitespace before the
|
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|
|
anticipated character.
|
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|
|
* config/tc-arm.c (parse_address_main): Delete skip of whitespace
|
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|
|
here as it is no longer needed.
|
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|
|
2013-01-07 01:50:21 +08:00
|
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|
|
2013-01-06 Andreas Schwab <schwab@linux-m68k.org>
|
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|
|
* doc/c-mips.texi (MIPS Opts): Fix use of @itemx.
|
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|
|
|
|
* doc/c-score.texi (SCORE-Opts): Likewise.
|
|
|
|
|
|
* doc/c-tic54x.texi (TIC54X-Directives): Likewise.
|
|
|
|
|
|
|
2013-01-05 01:22:53 +08:00
|
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|
2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
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|
|
* config/tc-mips.c: Add support for MIPS r5900.
|
|
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|
|
Add M_LQ_AB and M_SQ_AB to support large values for instructions
|
|
|
|
|
|
lq and sq.
|
|
|
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|
|
(can_swap_branch_p, get_append_method): Detect some conditional
|
|
|
|
|
|
short loops to fix a bug on the r5900 by NOP in the branch delay
|
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|
|
|
|
slot.
|
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|
|
(M_MUL): Support 3 operands in multu on r5900.
|
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|
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|
|
(M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
|
|
|
|
|
|
(s_mipsset): Force 32 bit floating point on r5900.
|
|
|
|
|
|
(mips_ip): Check parameter range of instructions mfps and mtps on
|
|
|
|
|
|
r5900.
|
|
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|
|
* configure.in: Detect CPU type when target string contains r5900
|
|
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|
|
(e.g. mips64r5900el-linux-gnu).
|
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|
|
2013-01-03 01:15:38 +08:00
|
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|
|
2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
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|
|
* as.c (parse_args): Update copyright year to 2013.
|
|
|
|
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|
|
2013-01-02 22:56:30 +08:00
|
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|
|
2013-01-02 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
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|
|
|
|
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|
|
* config/tc-aarch64.c (aarch64_cpus): Add entries for "cortex-a53"
|
|
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|
|
and "cortex57".
|
|
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|
|
2013-01-02 21:38:57 +08:00
|
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|
|
2013-01-02 Nick Clifton <nickc@redhat.com>
|
2012-12-21 00:19:53 +08:00
|
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|
|
2013-01-02 21:38:57 +08:00
|
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|
|
PR gas/14987
|
|
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|
|
* config/tc-arm.c (parse_address_main): Skip whitespace before a
|
|
|
|
|
|
closing bracket.
|
2012-12-21 00:19:53 +08:00
|
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|
|
2013-01-02 21:38:57 +08:00
|
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|
|
For older changes see ChangeLog-2012
|
2002-01-07 20:12:47 +08:00
|
|
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|
|
2013-01-02 21:38:57 +08:00
|
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|
|
Copyright (C) 2013 Free Software Foundation, Inc.
|
2012-12-10 20:48:03 +08:00
|
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|
Copying and distribution of this file, with or without modification,
|
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|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
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|
|
2002-01-07 20:12:47 +08:00
|
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|
|
Local Variables:
|
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|
|
mode: change-log
|
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|
|
left-margin: 8
|
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|
fill-column: 74
|
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version-control: never
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End:
|
