mirror of
https://sourceware.org/git/binutils-gdb.git
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213 lines
4.8 KiB
ArmAsm
213 lines
4.8 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32mult_dr_m_iutsh/c_dsp32mult_dr_m_iutsh.dsp
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// Spec Reference: dsp32mult single dr munop iu tu is ih
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0xfb235625;
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imm32 r1, 0x9fba5127;
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imm32 r2, 0xa3ff6725;
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imm32 r3, 0x0006f027;
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imm32 r4, 0xb0abcd29;
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imm32 r5, 0x1facef2b;
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imm32 r6, 0xc0fc002d;
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imm32 r7, 0xd24f702f;
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R4.L = R0.H * R0.L (TFU);
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R5.H = R0.L * R1.L (IU);
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R6.L = R1.L * R0.H (TFU);
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R7.L = R1.L * R1.L (TFU);
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R0.H = R0.L * R0.L (IU);
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R1.L = R0.L * R1.L (TFU);
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R2.L = R1.H * R0.L (IU);
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R3.H = R1.L * R1.L (TFU);
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CHECKREG r0, 0xFFFF5625;
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CHECKREG r1, 0x9FBA1B4E;
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CHECKREG r2, 0xA3FFFFFF;
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CHECKREG r3, 0x02E9F027;
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CHECKREG r4, 0xB0AB5482;
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CHECKREG r5, 0xFFFFEF2B;
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CHECKREG r6, 0xC0FC4F9C;
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CHECKREG r7, 0xD24F19B9;
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imm32 r0, 0xeb23a635;
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imm32 r1, 0x6fba5137;
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imm32 r2, 0x1324b7e5;
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imm32 r3, 0x9e060037;
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imm32 r4, 0x80ebcd39;
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imm32 r5, 0xb0aeef3b;
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imm32 r6, 0xa00ce03d;
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imm32 r7, 0x12467e03;
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R4.H = R2.L * R2.L (ISS2);
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R5.L = R2.L * R3.H (IH);
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R6.L = R3.H * R2.L (ISS2);
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R7.H = R3.L * R3.L (ISS2);
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R2.H = R2.L * R2.H (IH);
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R3.L = R2.H * R3.H (ISS2);
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R0.H = R3.L * R2.L (IH);
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R1.L = R3.L * R3.L (ISS2);
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CHECKREG r0, 0xDBF3A635;
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CHECKREG r1, 0x6FBA7FFF;
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CHECKREG r2, 0xFA9CB7E5;
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CHECKREG r3, 0x9E067FFF;
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CHECKREG r4, 0x7FFFCD39;
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CHECKREG r5, 0xB0AE1B99;
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CHECKREG r6, 0xA00C7FFF;
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CHECKREG r7, 0x17A27E03;
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imm32 r0, 0xdd235655;
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imm32 r1, 0xc4dd5157;
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imm32 r2, 0x6324d755;
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imm32 r3, 0x00060055;
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imm32 r4, 0x90dbc509;
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imm32 r5, 0x10adef5b;
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imm32 r6, 0xb00cd05d;
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imm32 r7, 0x12467d5f;
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R0.L = R4.L * R4.H (IU);
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R1.H = R4.H * R5.L (TFU);
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R2.L = R5.H * R4.L (ISS2);
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R3.L = R5.L * R5.L (IH);
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R4.H = R4.L * R4.H (ISS2);
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R5.L = R4.L * R5.H (TFU);
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R6.H = R5.H * R4.H (IU);
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R7.L = R5.H * R5.H (ISS2);
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CHECKREG r0, 0xDD23FFFF;
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CHECKREG r1, 0x876F5157;
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CHECKREG r2, 0x63248000;
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CHECKREG r3, 0x00060115;
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CHECKREG r4, 0x7FFFC509;
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CHECKREG r5, 0x10AD0CD5;
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CHECKREG r6, 0xFFFFD05D;
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CHECKREG r7, 0x12467FFF;
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imm32 r0, 0xcb235666;
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imm32 r1, 0xefba5166;
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imm32 r2, 0x1c248766;
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imm32 r3, 0xf0060066;
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imm32 r4, 0x90cb9d69;
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imm32 r5, 0x10acef6b;
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imm32 r6, 0x800cc06d;
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imm32 r7, 0x12467c6f;
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// test the unsigned U=1
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R0.L = R6.L * R6.L (TFU);
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R1.H = R6.H * R7.L (IH);
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R2.L = R7.L * R6.L (ISS2);
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R3.L = R7.L * R7.L (IH);
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R6.L = R6.L * R6.L (TFU);
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R7.L = R6.L * R7.L (IH);
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R4.L = R7.L * R6.L (TFU);
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R5.L = R7.L * R7.L (ISS2);
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CHECKREG r0, 0xCB2390A3;
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CHECKREG r1, 0xC1CE5166;
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CHECKREG r2, 0x1C248000;
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CHECKREG r3, 0xF0063C7C;
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CHECKREG r4, 0x90CB720D;
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CHECKREG r5, 0x10AC7FFF;
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CHECKREG r6, 0x800C90A3;
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CHECKREG r7, 0x1246C9DF;
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// mix order
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imm32 r0, 0xab23a675;
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imm32 r1, 0xcfba5127;
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imm32 r2, 0x13246705;
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imm32 r3, 0xe0060007;
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imm32 r4, 0x9eabcd09;
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imm32 r5, 0x10ecdfdb;
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imm32 r6, 0x000e000d;
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imm32 r7, 0x1246e00f;
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R0.H = R0.L * R7.H (IU);
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R1.L = R1.H * R6.H (ISS2);
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R2.L = R2.L * R5.L (IU);
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R3.H = R3.H * R4.H (ISS2);
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R4.L = R4.L * R3.H (IU);
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R5.L = R5.H * R2.H (ISS2);
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R6.H = R6.H * R1.L (IH);
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R7.L = R7.L * R0.H (IU);
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CHECKREG r0, 0xFFFFA675;
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CHECKREG r1, 0xCFBA8000;
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CHECKREG r2, 0x1324FFFF;
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CHECKREG r3, 0x7FFF0007;
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CHECKREG r4, 0x9EABFFFF;
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CHECKREG r5, 0x10EC7FFF;
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CHECKREG r6, 0xFFF9000D;
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CHECKREG r7, 0x1246FFFF;
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imm32 r0, 0x9b235a75;
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imm32 r1, 0xcfba5127;
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imm32 r2, 0x93246905;
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imm32 r3, 0x09060007;
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imm32 r4, 0x909bcd09;
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imm32 r5, 0x10a9e9db;
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imm32 r6, 0x000c9d0d;
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imm32 r7, 0x1246790f;
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R0.L = R7.L * R0.H (TFU);
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R1.L = R6.L * R1.L (TFU);
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R2.H = R5.L * R2.L (TFU);
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R3.L = R4.H * R3.L (TFU);
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R4.L = R3.H * R4.H (TFU);
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R5.H = R2.H * R5.L (TFU);
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R6.L = R1.H * R6.L (TFU);
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R7.L = R0.L * R7.L (TFU);
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CHECKREG r0, 0x9B23495C;
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CHECKREG r1, 0xCFBA31C9;
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CHECKREG r2, 0x5FEF6905;
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CHECKREG r3, 0x09060003;
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CHECKREG r4, 0x909B0518;
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CHECKREG r5, 0x57A2E9DB;
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CHECKREG r6, 0x000C7F6F;
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CHECKREG r7, 0x124622B0;
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imm32 r0, 0xa9235675;
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imm32 r1, 0xc8ba5127;
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imm32 r2, 0x13246705;
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imm32 r3, 0x08060007;
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imm32 r4, 0x908bcd09;
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imm32 r5, 0x10a88fdb;
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imm32 r6, 0x000c080d;
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imm32 r7, 0x1246708f;
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R2.L = R0.L * R6.L (IU);
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R3.L = R1.H * R7.L (IH);
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R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU);
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R1.H = R3.L * R1.L (IH);
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R4.L = R4.H * R2.L (IU);
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R5.L = R5.L * R3.L (ISS2);
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R6.L = R6.L * R4.L (IH);
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R7.H = R7.H * R5.L (IU);
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CHECKREG r0, 0xFFFFFFFF;
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CHECKREG r1, 0xF84C5127;
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CHECKREG r2, 0x1324FFFF;
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CHECKREG r3, 0x0806E7B2;
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CHECKREG r4, 0x908BFFFF;
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CHECKREG r5, 0x10A87FFF;
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CHECKREG r6, 0x000C0000;
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CHECKREG r7, 0xFFFF708F;
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imm32 r0, 0x7b235675;
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imm32 r1, 0xcfba5127;
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imm32 r2, 0x17246705;
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imm32 r3, 0x00760007;
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imm32 r4, 0x907bcd09;
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imm32 r5, 0x10a7efdb;
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imm32 r6, 0x000c700d;
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imm32 r7, 0x1246770f;
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R4.L = R5.L * R2.L (TFU);
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R6.L = R6.L * R3.H (ISS2);
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R0.H = R7.L * R4.H (ISS2);
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R1.L = R0.H * R5.L (ISS2);
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R2.L = R1.L * R6.L (IH);
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R5.L = R2.L * R7.H (TFU);
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R3.H = R3.H * R0.L (IH);
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R7.L = R4.H * R1.H (IU);
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CHECKREG r0, 0x80005675;
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CHECKREG r1, 0xCFBA7FFF;
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CHECKREG r2, 0x17243FFF;
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CHECKREG r3, 0x00280007;
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CHECKREG r4, 0x907B6085;
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CHECKREG r5, 0x10A70491;
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CHECKREG r6, 0x000C7FFF;
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CHECKREG r7, 0x1246FFFF;
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pass
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