2011-03-06 08:20:21 +08:00
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/* Blackfin External Bus Interface Unit (EBIU) DDR Controller (DDRC) Model.
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2013-01-01 14:41:43 +08:00
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Copyright (C) 2010-2013 Free Software Foundation, Inc.
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2011-03-06 08:20:21 +08:00
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_ebiu_ddrc.h"
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struct bfin_ebiu_ddrc
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{
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bu32 base, reg_size, bank_size;
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/* Order after here is important -- matches hardware MMR layout. */
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union {
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struct { bu32 ddrctl0, ddrctl1, ddrctl2, ddrctl3; };
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bu32 ddrctl[4];
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};
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bu32 ddrque, erradd;
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bu16 BFIN_MMR_16(errmst);
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bu16 BFIN_MMR_16(rstctl);
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bu32 ddrbrc[8], ddrbwc[8];
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bu32 ddracct, ddrtact, ddrarct;
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bu32 ddrgc[4];
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bu32 ddrmcen, ddrmccl;
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};
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#define mmr_base() offsetof(struct bfin_ebiu_ddrc, ddrctl0)
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#define mmr_offset(mmr) (offsetof(struct bfin_ebiu_ddrc, mmr) - mmr_base())
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2011-03-16 04:44:11 +08:00
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static const char * const mmr_names[] =
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{
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2011-03-06 08:20:21 +08:00
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"EBIU_DDRCTL0", "EBIU_DDRCTL1", "EBIU_DDRCTL2", "EBIU_DDRCTL3", "EBIU_DDRQUE",
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"EBIU_ERRADD", "EBIU_ERRMST", "EBIU_RSTCTL", "EBIU_DDRBRC0", "EBIU_DDRBRC1",
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"EBIU_DDRBRC2", "EBIU_DDRBRC3", "EBIU_DDRBRC4", "EBIU_DDRBRC5",
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"EBIU_DDRBRC6", "EBIU_DDRBRC7", "EBIU_DDRBWC0", "EBIU_DDRBWC1"
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"EBIU_DDRBWC2", "EBIU_DDRBWC3", "EBIU_DDRBWC4", "EBIU_DDRBWC5",
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"EBIU_DDRBWC6", "EBIU_DDRBWC7", "EBIU_DDRACCT", "EBIU_DDRTACT",
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"EBIU_ARCT", "EBIU_DDRGC0", "EBIU_DDRGC1", "EBIU_DDRGC2", "EBIU_DDRGC3",
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"EBIU_DDRMCEN", "EBIU_DDRMCCL",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static unsigned
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bfin_ebiu_ddrc_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_ebiu_ddrc *ddrc = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu16 *value16p;
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bu32 *value32p;
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void *valuep;
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if (nr_bytes == 4)
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value = dv_load_4 (source);
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else
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value = dv_load_2 (source);
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mmr_off = addr - ddrc->base;
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valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(errmst):
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case mmr_offset(rstctl):
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
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*value16p = value;
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break;
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default:
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dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
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*value32p = value;
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_ebiu_ddrc_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_ebiu_ddrc *ddrc = hw_data (me);
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bu32 mmr_off;
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bu32 *value32p;
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bu16 *value16p;
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void *valuep;
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mmr_off = addr - ddrc->base;
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valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(errmst):
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case mmr_offset(rstctl):
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
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dv_store_2 (dest, *value16p);
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break;
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default:
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dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
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dv_store_4 (dest, *value32p);
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break;
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}
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return nr_bytes;
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}
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static void
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attach_bfin_ebiu_ddrc_regs (struct hw *me, struct bfin_ebiu_ddrc *ddrc)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_EBIU_DDRC_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EBIU_DDRC_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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ddrc->base = attach_address;
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}
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static void
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bfin_ebiu_ddrc_finish (struct hw *me)
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{
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struct bfin_ebiu_ddrc *ddrc;
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ddrc = HW_ZALLOC (me, struct bfin_ebiu_ddrc);
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set_hw_data (me, ddrc);
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set_hw_io_read_buffer (me, bfin_ebiu_ddrc_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_ebiu_ddrc_io_write_buffer);
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attach_bfin_ebiu_ddrc_regs (me, ddrc);
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/* Initialize the DDRC. */
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ddrc->ddrctl0 = 0x098E8411;
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ddrc->ddrctl1 = 0x10026223;
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ddrc->ddrctl2 = 0x00000021;
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ddrc->ddrctl3 = 0x00000003; /* XXX: MDDR is 0x20 ... */
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ddrc->ddrque = 0x00001115;
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ddrc->rstctl = 0x0002;
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}
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2011-03-16 04:55:11 +08:00
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const struct hw_descriptor dv_bfin_ebiu_ddrc_descriptor[] =
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{
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2011-03-06 08:20:21 +08:00
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{"bfin_ebiu_ddrc", bfin_ebiu_ddrc_finish,},
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{NULL, NULL},
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};
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