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67 lines
1.9 KiB
Plaintext
67 lines
1.9 KiB
Plaintext
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# frv testcase to generate compound exception
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# mach: fr500 frv
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.include "testutils.inc"
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start
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.global align
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align:
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr17
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inc_gr_immed 0x200,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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set_spr_immed 128,lcr
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set_spr_addr ok1,lr
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or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception
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set_psr_et 1
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set_gr_immed 0,gr15
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set_fr_iimmed 0x7f7f,0xffff,fr0
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set_fr_iimmed 0x0000,0x0000,fr1
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and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned
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set_gr_addr store,gr16
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set_gr_addr dividei,gr17
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set_gr_immed 0xdeadbeef,gr8
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inc_gr_immed 2,sp ; misalign
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store: sti.p gr8,@(sp,0) ; misaligned write
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dividef:fdivs.p fr0,fr1,fr2 ; fp_exception
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dividei:sdiv gr1,gr0,gr1 ; division exception
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test_gr_immed 1,gr15
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pass
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; exception handler
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ok1:
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; check interrupt on store
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test_spr_immed 0x102,esfr1 ; esr8 and esr1 are active
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test_spr_gr epcr8,gr16
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test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid
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test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set
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test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set
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test_spr_gr ear8,sp
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test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set
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test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3
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test_spr_gr edr3,gr8 ; edr3 is set
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; check on fp_exception
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test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set
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test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
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test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear
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test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set
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test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set
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test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set
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test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set
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test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set
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test_spr_immed 0x05e40241,fqop2 ; fq2.opc
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; check interrupt on dividei
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test_spr_gr epcr1,gr17
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test_spr_bits 0x0001,0,0x1,esr1 ; esr1 is valid
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test_spr_bits 0x003e,1,0x13,esr1 ; esr1.ec is set
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inc_gr_immed 1,gr15
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rett 0
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fail
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