mirror of
https://sourceware.org/git/binutils-gdb.git
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215 lines
4.4 KiB
ArmAsm
215 lines
4.4 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp
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// Spec Reference: dsp32shift signbits dregs
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x88880000;
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imm32 r1, 0x34560001;
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imm32 r2, 0x08000002;
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imm32 r3, 0x08000003;
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imm32 r4, 0x08000004;
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imm32 r5, 0x08000005;
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imm32 r6, 0x08000006;
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imm32 r7, 0x08000007;
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R7.L = SIGNBITS R0;
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R1.L = SIGNBITS R0;
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R2.L = SIGNBITS R0;
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R3.L = SIGNBITS R0;
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R4.L = SIGNBITS R0;
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R5.L = SIGNBITS R0;
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R6.L = SIGNBITS R0;
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R0.L = SIGNBITS R0;
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CHECKREG r0, 0x88880000;
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CHECKREG r1, 0x34560000;
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CHECKREG r2, 0x08000000;
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CHECKREG r3, 0x08000000;
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CHECKREG r4, 0x08000000;
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CHECKREG r5, 0x08000000;
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CHECKREG r6, 0x08000000;
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CHECKREG r7, 0x08000000;
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imm32 r0, 0x9999001E;
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imm32 r1, 0x0000001E;
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imm32 r2, 0x0000001E;
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imm32 r3, 0x0000001E;
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imm32 r4, 0x0000001E;
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imm32 r5, 0x0000001E;
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imm32 r6, 0x0000001E;
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imm32 r7, 0x0000001E;
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R0.L = SIGNBITS R1;
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R7.L = SIGNBITS R1;
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R2.L = SIGNBITS R1;
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R3.L = SIGNBITS R1;
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R4.L = SIGNBITS R1;
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R5.L = SIGNBITS R1;
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R6.L = SIGNBITS R1;
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R1.L = SIGNBITS R1;
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CHECKREG r0, 0x9999001A;
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CHECKREG r1, 0x0000001A;
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CHECKREG r2, 0x0000001A;
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CHECKREG r3, 0x0000001A;
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CHECKREG r4, 0x0000001A;
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CHECKREG r5, 0x0000001A;
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CHECKREG r6, 0x0000001A;
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CHECKREG r7, 0x0000001A;
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imm32 r0, 0x0aaae001;
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imm32 r1, 0x0000e001;
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imm32 r2, 0xaaaa000f;
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imm32 r3, 0x0a00e003;
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imm32 r4, 0x00a0e004;
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imm32 r5, 0x00a0e005;
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imm32 r6, 0x0a00e006;
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imm32 r7, 0x0b00e007;
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R0.L = SIGNBITS R2;
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R1.L = SIGNBITS R2;
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R7.L = SIGNBITS R2;
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R3.L = SIGNBITS R2;
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R4.L = SIGNBITS R2;
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R5.L = SIGNBITS R2;
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R6.L = SIGNBITS R2;
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R2.L = SIGNBITS R2;
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CHECKREG r0, 0x0AAA0000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0xAAAA0000;
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CHECKREG r3, 0x0A000000;
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CHECKREG r4, 0x00A00000;
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CHECKREG r5, 0x00A00000;
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CHECKREG r6, 0x0A000000;
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CHECKREG r7, 0x0B000000;
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imm32 r0, 0x0b00f001;
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imm32 r1, 0x0a00f001;
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imm32 r2, 0x0b00f002;
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imm32 r3, 0xbbbb0010;
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imm32 r4, 0x0b00f004;
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imm32 r5, 0x0b00f005;
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imm32 r6, 0x0b00f006;
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imm32 r7, 0x00b0f007;
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R0.L = SIGNBITS R3;
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R1.L = SIGNBITS R3;
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R2.L = SIGNBITS R3;
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R7.L = SIGNBITS R3;
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R4.L = SIGNBITS R3;
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R5.L = SIGNBITS R3;
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R6.L = SIGNBITS R3;
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R3.L = SIGNBITS R3;
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CHECKREG r0, 0x0B000000;
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CHECKREG r1, 0x0A000000;
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CHECKREG r2, 0x0B000000;
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CHECKREG r3, 0xBBBB0000;
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CHECKREG r4, 0x0B000000;
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CHECKREG r5, 0x0B000000;
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CHECKREG r6, 0x0B000000;
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CHECKREG r7, 0x00B00000;
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imm32 r0, 0x00000000;
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imm32 r1, 0x00010000;
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imm32 r2, 0x00020000;
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imm32 r3, 0x00030000;
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imm32 r4, 0xcccc0000;
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imm32 r5, 0x00050000;
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imm32 r6, 0x00060000;
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imm32 r7, 0x00070000;
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R0.L = SIGNBITS R4;
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R1.L = SIGNBITS R4;
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R2.L = SIGNBITS R4;
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R3.L = SIGNBITS R4;
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R7.L = SIGNBITS R4;
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R5.L = SIGNBITS R4;
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R6.L = SIGNBITS R4;
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R4.L = SIGNBITS R4;
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00010001;
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CHECKREG r2, 0x00020001;
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CHECKREG r3, 0x00030001;
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CHECKREG r4, 0xCCCC0001;
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CHECKREG r5, 0x00050001;
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CHECKREG r6, 0x00060001;
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CHECKREG r7, 0x00070001;
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imm32 r0, 0xa0010000;
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imm32 r1, 0x00010001;
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imm32 r2, 0xa0020000;
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imm32 r3, 0xa0030000;
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imm32 r4, 0xa0040000;
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imm32 r5, 0xdddd0000;
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imm32 r6, 0xa0060000;
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imm32 r7, 0xa0070000;
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R0.L = SIGNBITS R5;
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R1.L = SIGNBITS R5;
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R2.L = SIGNBITS R5;
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R3.L = SIGNBITS R5;
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R4.L = SIGNBITS R5;
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R7.L = SIGNBITS R5;
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R6.L = SIGNBITS R5;
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R5.L = SIGNBITS R5;
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CHECKREG r0, 0xA0010001;
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CHECKREG r1, 0x00010001;
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CHECKREG r2, 0xA0020001;
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CHECKREG r3, 0xA0030001;
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CHECKREG r4, 0xA0040001;
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CHECKREG r5, 0xDDDD0001;
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CHECKREG r6, 0xA0060001;
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CHECKREG r7, 0xA0070001;
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imm32 r0, 0xb0010000;
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imm32 r1, 0xb0010000;
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imm32 r2, 0xb002000f;
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imm32 r3, 0xb0030000;
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imm32 r4, 0xb0040000;
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imm32 r5, 0xb0050000;
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imm32 r6, 0xeeee0000;
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imm32 r7, 0xb0070000;
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R0.L = SIGNBITS R6;
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R1.L = SIGNBITS R6;
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R2.L = SIGNBITS R6;
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R3.L = SIGNBITS R6;
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R4.L = SIGNBITS R6;
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R5.L = SIGNBITS R6;
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R7.L = SIGNBITS R6;
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R6.L = SIGNBITS R6;
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CHECKREG r0, 0xB0010002;
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CHECKREG r1, 0xB0010002;
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CHECKREG r2, 0xB0020002;
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CHECKREG r3, 0xB0030002;
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CHECKREG r4, 0xB0040002;
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CHECKREG r5, 0xB0050002;
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CHECKREG r6, 0xEEEE0002;
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CHECKREG r7, 0xB0070002;
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imm32 r0, 0xd0010000;
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imm32 r1, 0xd0010000;
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imm32 r2, 0xd0020000;
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imm32 r3, 0xd0030010;
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imm32 r4, 0xd0040000;
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imm32 r5, 0xd0050000;
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imm32 r6, 0xd0060000;
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imm32 r7, 0xffff0000;
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R0.L = SIGNBITS R7;
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R1.L = SIGNBITS R7;
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R2.L = SIGNBITS R7;
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R3.L = SIGNBITS R7;
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R4.L = SIGNBITS R7;
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R5.L = SIGNBITS R7;
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R6.L = SIGNBITS R7;
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R7.L = SIGNBITS R7;
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CHECKREG r0, 0xD001000F;
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CHECKREG r1, 0xD001000F;
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CHECKREG r2, 0xD002000F;
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CHECKREG r3, 0xD003000F;
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CHECKREG r4, 0xD004000F;
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CHECKREG r5, 0xD005000F;
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CHECKREG r6, 0xD006000F;
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CHECKREG r7, 0xFFFF000F;
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pass
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