2011-06-05 01:44:22 +08:00
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//Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp
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# mach: bfin
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.include "testutils.inc"
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start
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// Spec Reference: dsp32shiftimm ashift: ashift saturated
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imm32 r0, 0x81230001;
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imm32 r1, 0x19345678;
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imm32 r2, 0x23c56789;
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imm32 r3, 0x3ed6789a;
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imm32 r4, 0x85d789ab;
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imm32 r5, 0x967f9abc;
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imm32 r6, 0xa789bbcd;
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imm32 r7, 0xb891acde;
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R0 = R0 << 0 (S);
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R1 = R1 << 3 (S);
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R2 = R2 << 7 (S);
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R3 = R3 << 8 (S);
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R4 = R4 << 15 (S);
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R5 = R5 << 24 (S);
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R6 = R6 << 31 (S);
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R7 = R7 << 20 (S);
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CHECKREG r0, 0x81230001;
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CHECKREG r1, 0x7FFFFFFF;
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CHECKREG r2, 0x7FFFFFFF;
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CHECKREG r3, 0x7FFFFFFF;
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CHECKREG r4, 0x80000000;
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CHECKREG r5, 0x80000000;
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CHECKREG r6, 0x80000000;
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CHECKREG r7, 0x80000000;
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2012-03-25 14:43:43 +08:00
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imm32 r0, 0xa1230001;
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2011-06-05 01:44:22 +08:00
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imm32 r1, 0x1e345678;
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imm32 r2, 0x23f56789;
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imm32 r3, 0x34db789a;
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imm32 r4, 0x85a7a9ab;
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imm32 r5, 0x967c9abc;
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imm32 r6, 0xa78dabcd;
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imm32 r7, 0xb8914cde;
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R6 = R0 >>> 1;
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R7 = R1 >>> 3;
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R0 = R2 >>> 7;
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R1 = R3 >>> 8;
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R2 = R4 >>> 15;
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R3 = R5 >>> 24;
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R4 = R6 >>> 31;
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R5 = R7 >>> 20;
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CHECKREG r0, 0x0047EACF;
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CHECKREG r1, 0x0034DB78;
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CHECKREG r2, 0xFFFF0B4F;
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CHECKREG r3, 0xFFFFFF96;
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CHECKREG r4, 0xFFFFFFFF;
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CHECKREG r5, 0x0000003C;
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CHECKREG r6, 0xD0918000;
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CHECKREG r7, 0x03C68ACF;
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pass
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