mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-21 04:42:53 +08:00
262 lines
7.5 KiB
ArmAsm
262 lines
7.5 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft_x/c_dsp32alu_rrppmm_sft_x.dsp
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// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, << X
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# mach: bfin
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.include "testutils.inc"
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start
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R0 = 0;
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ASTAT = R0;
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imm32 r0, 0x95679911;
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imm32 r1, 0x2789ab1d;
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imm32 r2, 0x34945515;
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imm32 r3, 0x46967717;
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imm32 r4, 0x5597891b;
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imm32 r5, 0x6989ab1d;
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imm32 r6, 0x94445515;
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imm32 r7, 0x96667777;
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R0 = R0 +|+ R0, R7 = R0 -|- R0 (CO , ASR);
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R1 = R0 +|+ R1, R6 = R0 -|- R1 (CO , ASL);
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R2 = R0 +|+ R2, R5 = R0 -|- R2 (CO , ASR);
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R3 = R0 +|+ R3, R4 = R0 -|- R3 (CO , ASR);
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R4 = R0 +|+ R4, R3 = R0 -|- R4 (CO , ASL);
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R5 = R0 +|+ R5, R2 = R0 -|- R5 (CO , ASR);
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R6 = R0 +|+ R6, R1 = R0 -|- R6 (CO , ASL);
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R7 = R0 +|+ R7, R0 = R0 -|- R7 (CO , ASR);
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CHECKREG r0, 0xcC88cAB3;
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CHECKREG r1, 0x7AAA72FE;
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CHECKREG r2, 0xf454f9B4;
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CHECKREG r3, 0xe35208D4;
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CHECKREG r4, 0x4CC880F2;
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CHECKREG r5, 0x9BB2a4BD;
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CHECKREG r6, 0xE29EE99A;
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CHECKREG r7, 0xcAB3cC88;
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imm32 r0, 0x11678911;
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imm32 r1, 0xa719ab1d;
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imm32 r2, 0x3a415515;
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imm32 r3, 0x46a67717;
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imm32 r4, 0x556a891b;
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imm32 r5, 0x6789ab1d;
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imm32 r6, 0x74445a15;
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imm32 r7, 0x866677a7;
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R0 = R1 +|+ R0, R7 = R1 -|- R0 (CO , ASR);
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R1 = R1 +|+ R1, R6 = R1 -|- R1 (CO , ASR);
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R2 = R1 +|+ R2, R5 = R1 -|- R2 (CO , ASL);
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R3 = R1 +|+ R3, R4 = R1 -|- R3 (CO , ASR);
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R4 = R1 +|+ R4, R3 = R1 -|- R4 (CO , ASR);
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R5 = R1 +|+ R5, R2 = R1 -|- R5 (CO , ASR);
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R6 = R1 +|+ R6, R1 = R1 -|- R6 (CO , ASL);
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R7 = R1 +|+ R7, R0 = R1 -|- R7 (CO , ASR);
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CHECKREG r0, 0x41AC229A;
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CHECKREG r1, 0x563A4E32;
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CHECKREG r2, 0xe8B6fD84;
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CHECKREG r3, 0xfD72068B;
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CHECKREG r4, 0xa08EaDAB;
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CHECKREG r5, 0xa994c266;
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CHECKREG r6, 0x4E32563A;
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CHECKREG r7, 0x33A00C85;
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imm32 r0, 0xb567891b;
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imm32 r1, 0x2b89abbd;
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imm32 r2, 0x34b45b15;
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imm32 r3, 0x466bb717;
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imm32 r4, 0x556bb91b;
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imm32 r5, 0x67b9ab1d;
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imm32 r6, 0x7b4455b5;
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imm32 r7, 0xb666777b;
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R0 = R2 +|+ R0, R7 = R2 -|- R0 (CO , ASR);
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R1 = R2 +|+ R1, R6 = R2 -|- R1 (CO , ASR);
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R2 = R2 +|+ R2, R5 = R2 -|- R2 (CO , ASR);
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R3 = R2 +|+ R3, R4 = R2 -|- R3 (CO , ASL);
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R4 = R2 +|+ R4, R3 = R2 -|- R4 (CO , ASR);
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R5 = R2 +|+ R5, R2 = R2 -|- R5 (CO , ASR);
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R6 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASL);
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R7 = R2 +|+ R7, R0 = R2 -|- R7 (CO , ASR);
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CHECKREG r0, 0xED5Ae246;
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CHECKREG r1, 0x2B8AaBBC;
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CHECKREG r2, 0x2D8A1A5A;
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CHECKREG r3, 0x3F41F65C;
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CHECKREG r4, 0x3E581BD3;
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CHECKREG r5, 0x1A5A2D8A;
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CHECKREG r6, 0x0A6C3DDE;
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CHECKREG r7, 0x4B432D00;
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imm32 r0, 0xbc678c11;
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imm32 r1, 0x27c9cb1d;
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imm32 r2, 0x344c5515;
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imm32 r3, 0x46c6c717;
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imm32 r4, 0x55678c1b;
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imm32 r5, 0x6c89abcd;
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imm32 r6, 0x7444551c;
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imm32 r7, 0x8c667777;
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R0 = R3 +|+ R0, R7 = R3 -|- R0 (CO , ASL);
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R1 = R3 +|+ R1, R6 = R3 -|- R1 (CO , ASR);
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R2 = R3 +|+ R2, R5 = R3 -|- R2 (CO , ASR);
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R3 = R3 +|+ R3, R4 = R3 -|- R3 (CO , ASR);
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R4 = R3 +|+ R4, R3 = R3 -|- R4 (CO , ASL);
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R5 = R3 +|+ R5, R2 = R3 -|- R5 (CO , ASR);
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R6 = R3 +|+ R6, R1 = R3 -|- R6 (CO , ASR);
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R7 = R3 +|+ R7, R0 = R3 -|- R7 (CO , ASL);
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CHECKREG r0, 0xF19C3044;
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CHECKREG r1, 0xbF07C818;
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CHECKREG r2, 0xC227eA96;
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CHECKREG r3, 0x8E2E8D8C;
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CHECKREG r4, 0x8D8C8E2E;
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CHECKREG r5, 0xa397CB64;
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CHECKREG r6, 0xC615CE85;
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CHECKREG r7, 0x08744494;
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imm32 r0, 0xd56789d1;
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imm32 r1, 0x2d89abdd;
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imm32 r2, 0x34d455d5;
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imm32 r3, 0x4d667717;
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imm32 r4, 0x5dd7891b;
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imm32 r5, 0x6789ab1d;
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imm32 r6, 0xd44d5515;
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imm32 r7, 0xd666d777;
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R0 = R4 +|+ R0, R7 = R4 -|- R0 (CO , ASR);
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R1 = R4 +|+ R1, R6 = R4 -|- R1 (CO , ASR);
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R2 = R4 +|+ R2, R5 = R4 -|- R2 (CO , ASR);
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R3 = R4 +|+ R3, R4 = R4 -|- R3 (CO , ASL);
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R4 = R4 +|+ R4, R3 = R4 -|- R4 (CO , ASR);
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R5 = R4 +|+ R5, R2 = R4 -|- R5 (CO , ASL);
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R6 = R4 +|+ R6, R1 = R4 -|- R6 (CO , ASR);
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R7 = R4 +|+ R7, R0 = R4 -|- R7 (CO , ASR);
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CHECKREG r0, 0xeE551231;
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CHECKREG r1, 0x045D1AB4;
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CHECKREG r2, 0x18C214CA;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x240820E2;
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CHECKREG r5, 0x7B566AC6;
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CHECKREG r6, 0x09531C84;
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CHECKREG r7, 0x11D6328D;
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imm32 r0, 0xc567a911;
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imm32 r1, 0x278aab1d;
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imm32 r2, 0x3c445515;
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imm32 r3, 0x46a67717;
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imm32 r4, 0x55c7891b;
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imm32 r5, 0x6a8cab1d;
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imm32 r6, 0x7444c515;
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imm32 r7, 0xa6667c77;
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R0 = R5 +|+ R0, R7 = R5 -|- R0 (CO , ASR);
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R1 = R5 +|+ R1, R6 = R5 -|- R1 (CO , ASL);
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R2 = R5 +|+ R2, R5 = R5 -|- R2 (CO , ASR);
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R3 = R5 +|+ R3, R4 = R5 -|- R3 (CO , ASR);
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R4 = R5 +|+ R4, R3 = R5 -|- R4 (CO , ASR);
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R5 = R5 +|+ R5, R2 = R5 -|- R5 (CO , ASL);
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R6 = R5 +|+ R6, R1 = R5 -|- R6 (CO , ASR);
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R7 = R5 +|+ R7, R0 = R5 -|- R7 (CO , ASR);
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CHECKREG r0, 0x04FFD585;
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CHECKREG r1, 0x6B46D608;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x327AeD7F;
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CHECKREG r4, 0xbD85e4A9;
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CHECKREG r5, 0xAC105C90;
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CHECKREG r6, 0xD608F14A;
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CHECKREG r7, 0xD68B5791;
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imm32 r0, 0xd5678911;
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imm32 r1, 0x2ddddd1d;
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imm32 r2, 0x34ddd515;
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imm32 r3, 0x46d67717;
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imm32 r4, 0x5d6d891b;
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imm32 r5, 0x6789db1d;
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imm32 r6, 0x74445d15;
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imm32 r7, 0xd66677d7;
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R0 = R6 +|+ R0, R7 = R6 -|- R0 (CO , ASR);
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R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASR);
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R2 = R6 +|+ R2, R5 = R6 -|- R2 (CO , ASR);
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R3 = R6 +|+ R3, R4 = R6 -|- R3 (CO , ASL);
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R4 = R6 +|+ R4, R3 = R6 -|- R4 (CO , ASR);
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R5 = R6 +|+ R5, R2 = R6 -|- R5 (CO , ASR);
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R6 = R6 +|+ R6, R1 = R6 -|- R6 (CO , ASL);
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R7 = R6 +|+ R7, R0 = R6 -|- R7 (CO , ASR);
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CHECKREG r0, 0x9EAFcAF7;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x0ED20C76;
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CHECKREG r3, 0x1873F3E2;
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CHECKREG r4, 0x4C1A0ABF;
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CHECKREG r5, 0x33851461;
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CHECKREG r6, 0xFFF08CCC;
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CHECKREG r7, 0x34F9eE1D;
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imm32 r0, 0xf567a911;
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imm32 r1, 0x2f8aab1d;
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imm32 r2, 0x34a45515;
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imm32 r3, 0x4a6f7717;
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imm32 r4, 0x5567f91b;
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imm32 r5, 0xa789af1d;
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imm32 r6, 0x74445515;
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imm32 r7, 0x866677f7;
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R0 = R7 +|+ R0, R7 = R7 -|- R0 (CO , ASR);
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R1 = R7 +|+ R1, R6 = R7 -|- R1 (CO , ASL);
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R2 = R7 +|+ R2, R5 = R7 -|- R2 (CO , ASR);
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R3 = R7 +|+ R3, R4 = R7 -|- R3 (CO , ASR);
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R4 = R7 +|+ R4, R3 = R7 -|- R4 (CO , ASL);
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R5 = R7 +|+ R5, R2 = R7 -|- R5 (CO , ASL);
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R6 = R7 +|+ R6, R1 = R7 -|- R6 (CO , ASR);
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R7 = R7 +|+ R7, R0 = R7 -|- R7 (CO , ASL);
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0xaC561657;
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CHECKREG r2, 0x5E305B7C;
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CHECKREG r3, 0x73FA7D7E;
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CHECKREG r4, 0x204EaE02;
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CHECKREG r5, 0x4250c3CC;
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CHECKREG r6, 0x511B1C28;
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CHECKREG r7, 0x9DCC21FC;
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imm32 r0, 0xe5678911;
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imm32 r1, 0x2e89ab1d;
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imm32 r2, 0x34e45515;
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imm32 r3, 0x46667717;
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imm32 r4, 0x556e891b;
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imm32 r5, 0x6789ab1d;
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imm32 r6, 0x7444e515;
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imm32 r7, 0x86667e77;
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R4 = R2 +|+ R5, R3 = R2 -|- R5 (CO , ASR);
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R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO , ASL);
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R2 = R6 +|+ R2, R0 = R6 -|- R2 (CO , ASL);
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R3 = R4 +|+ R0, R2 = R4 -|- R0 (CO , ASR);
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R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO , ASL);
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R6 = R1 +|+ R7, R1 = R1 -|- R7 (CO , ASL);
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R5 = R0 +|+ R4, R7 = R0 -|- R4 (CO , ASR);
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R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO , ASR);
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CHECKREG r0, 0x20007EC0;
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CHECKREG r1, 0xfF9258EB;
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CHECKREG r2, 0xC0AC171B;
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CHECKREG r3, 0x371B3F6C;
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CHECKREG r4, 0xE6813788;
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CHECKREG r5, 0x371B3F6C;
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CHECKREG r6, 0x47BAE46A;
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CHECKREG r7, 0x3F53e8E5;
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imm32 r0, 0xd5678911;
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imm32 r1, 0xff89ab1d;
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imm32 r2, 0x34f45515;
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imm32 r3, 0x46667717;
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imm32 r4, 0x556f891b;
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imm32 r5, 0x6789fb1d;
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imm32 r6, 0x74445f15;
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imm32 r7, 0x866677f7;
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R4 = R3 +|+ R3, R5 = R3 -|- R3 (CO , ASR);
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R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASL);
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R6 = R1 +|+ R4, R4 = R1 -|- R4 (CO , ASL);
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R7 = R4 +|+ R2, R0 = R4 -|- R2 (CO , ASR);
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R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASR);
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R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO , ASL);
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R5 = R7 +|+ R7, R3 = R7 -|- R7 (CO , ASL);
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R0 = R0 +|+ R0, R2 = R0 -|- R0 (CO , ASR);
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CHECKREG r0, 0xF6A902D3;
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CHECKREG r1, 0x1F0FEC7A;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x3A9A4268;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x5C0016F6;
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CHECKREG r7, 0x00000000;
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pass
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